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| author | Craig Topper <craig.topper@gmail.com> | 2014-04-04 05:16:06 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2014-04-04 05:16:06 +0000 |
| commit | 840beec2d0855db9165c02bc29a79af8e357fc24 (patch) | |
| tree | cc21088e8d06f5c3158cd6fc7e00b483c9f0a817 /llvm/lib/CodeGen/TargetRegisterInfo.cpp | |
| parent | 79ed5d44e715537a933c399885dce58c7d877f73 (diff) | |
| download | llvm-840beec2d0855db9165c02bc29a79af8e357fc24.zip llvm-840beec2d0855db9165c02bc29a79af8e357fc24.tar.gz llvm-840beec2d0855db9165c02bc29a79af8e357fc24.tar.bz2 | |
Make consistent use of MCPhysReg instead of uint16_t throughout the tree.
llvm-svn: 205610
Diffstat (limited to 'llvm/lib/CodeGen/TargetRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/TargetRegisterInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp index 5a15243..b760287 100644 --- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp +++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp @@ -130,7 +130,7 @@ TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const { static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R){ assert(RC->isAllocatable() && "invalid for nonallocatable sets"); - ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF); + ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF); for (unsigned i = 0; i != Order.size(); ++i) R.set(Order[i]); } |