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authorDjordje Todorovic <djordje.todorovic@rt-rk.com>2020-02-05 09:50:05 +0100
committerDjordje Todorovic <djordje.todorovic@rt-rk.com>2020-02-05 10:03:14 +0100
commitde90d73e030c5c98d7557c8bbf9b60b4b0e209cc (patch)
treeced2ee1ca5547210de7f8f24b9495fee819646f9 /llvm/lib/CodeGen/TargetInstrInfo.cpp
parent6e8d6bc9ec8739ec22b73a23f740f171f452e234 (diff)
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[DebugInfo] Avoid the call site param for mem instrs with multiple defs
We currently only handle mem instructions with a single define. Avoid the call site parameter debug info when we find the case with multiple defs, rather than throwing an assert. Differential Revision: https://reviews.llvm.org/D73954
Diffstat (limited to 'llvm/lib/CodeGen/TargetInstrInfo.cpp')
-rw-r--r--llvm/lib/CodeGen/TargetInstrInfo.cpp10
1 files changed, 8 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index fda2098..3c4f884 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1178,8 +1178,14 @@ TargetInstrInfo::describeLoadedValue(const MachineInstr &MI,
if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, TRI))
return None;
- assert(MI.getNumExplicitDefs() == 1 &&
- "Can currently only handle mem instructions with a single define");
+ // TODO: Can currently only handle mem instructions with a single define.
+ // An example from the x86 target:
+ // ...
+ // DIV64m $rsp, 1, $noreg, 24, $noreg, implicit-def dead $rax, implicit-def $rdx
+ // ...
+ //
+ if (MI.getNumExplicitDefs() != 1)
+ return None;
// TODO: In what way do we need to take Reg into consideration here?