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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2020-01-28 14:14:37 -0800 |
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| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2020-01-29 08:01:29 -0800 |
| commit | c2ad7ee1a9add223f8c9cdb5761c71cfdcda9136 (patch) | |
| tree | 703660ee7b9d1b551a29e0afe4bf9117ac654fbb /llvm/lib/CodeGen/MachineScheduler.cpp | |
| parent | f717483acd5e7d278ecd54ae80d2c1138fb51d06 (diff) | |
| download | llvm-c2ad7ee1a9add223f8c9cdb5761c71cfdcda9136.zip llvm-c2ad7ee1a9add223f8c9cdb5761c71cfdcda9136.tar.gz llvm-c2ad7ee1a9add223f8c9cdb5761c71cfdcda9136.tar.bz2 | |
[AMDGPU] override isHighLatencyDef
SIMachineScheduler uses isHighLatencyInstruction with the same
sematincs, but TargetInstrInfo has virtual isHighLatencyDef
method, so override it instead.
Added FLAT to the list of high latency opcodes and a check for
mayLoad since stores are not technically high latency in terms
of data dependency.
This change did not produce any visible impact on our tests.
Differential Revision: https://reviews.llvm.org/D73582
Diffstat (limited to 'llvm/lib/CodeGen/MachineScheduler.cpp')
0 files changed, 0 insertions, 0 deletions