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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-02-18 09:34:31 -0500 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-02-21 12:14:18 -0500 |
| commit | 60023e347116e5004295e8c7f2f09cc1855d4d84 (patch) | |
| tree | 64872e4a183d1c59bc4ffaac5e456dd1697341fd /llvm/lib/CodeGen/MachineBlockFrequencyInfo.cpp | |
| parent | db9c40f5624e6d55e0cbafe3f3980a7223e197c4 (diff) | |
| download | llvm-60023e347116e5004295e8c7f2f09cc1855d4d84.zip llvm-60023e347116e5004295e8c7f2f09cc1855d4d84.tar.gz llvm-60023e347116e5004295e8c7f2f09cc1855d4d84.tar.bz2 | |
AMDGPU: Use default operand for VOP3P clamp
We don't use this, and matching from the def doesn't make much sense.
There are multiple tablegen bugs with default operand
handling. undef_tied_input should work to handle the vdst_in
correctly, but this breaks the operand register class constraint which
it should be able to infer.
Diffstat (limited to 'llvm/lib/CodeGen/MachineBlockFrequencyInfo.cpp')
0 files changed, 0 insertions, 0 deletions