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| author | Aiden Grossman <aidengrossman@google.com> | 2024-11-24 16:58:16 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-24 16:58:16 -0800 |
| commit | 512dc5cb32e65081f4481afc757beade9bd64d04 (patch) | |
| tree | e95d298cad9482dd6b3736608cf99e4f30159c57 /llvm/lib/CodeGen/ExpandVectorPredication.cpp | |
| parent | 095f489757ead08184dd340f14a7b6158db6b0a3 (diff) | |
| download | llvm-512dc5cb32e65081f4481afc757beade9bd64d04.zip llvm-512dc5cb32e65081f4481afc757beade9bd64d04.tar.gz llvm-512dc5cb32e65081f4481afc757beade9bd64d04.tar.bz2 | |
[X86] Swap ports 10 and 11 in Alder Lake Scheduling Model (#117466)
Based on https://github.com/intel/perfmon/issues/149, the documentation
is incorrect and the pfm counter names are actually correct. This patch
adjusts the Alder Lake scheduling model to match the performance counter
naming/ correct naming that will soon be reflected in the optimization
manual.
This fixes part of #117360.
Diffstat (limited to 'llvm/lib/CodeGen/ExpandVectorPredication.cpp')
0 files changed, 0 insertions, 0 deletions