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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2024-11-26 19:38:23 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-26 19:38:23 -0500 |
| commit | c8ee1ee0571c5e49bee42983a8b9d8db0243c001 (patch) | |
| tree | 2acb16a088208697c99a1c6e974c754918d5b737 /llvm/lib/Bitcode/Writer/BitcodeWriterPass.cpp | |
| parent | 065dc93d9626930b48f8e88b1e0a18c746951ce0 (diff) | |
| download | llvm-c8ee1ee0571c5e49bee42983a8b9d8db0243c001.zip llvm-c8ee1ee0571c5e49bee42983a8b9d8db0243c001.tar.gz llvm-c8ee1ee0571c5e49bee42983a8b9d8db0243c001.tar.bz2 | |
AMDGPU: Builtin & CodeGen support for v_cvt_scalef32_pk_fp4_{f|bf}16 for gfx950 (#117794)
These instructions have non-standard use of OPSEL bits to select
dest write byte. The src2_modifiers operand is used without having
its corresponding src2 operand by introducing dummy src2.
OPSEL ASM OPSEL Syntax: opsel:[a,b,c,d]
a & b are meaningless, c & d together decides byte to write in dst reg.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap@amd.com>
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriterPass.cpp')
0 files changed, 0 insertions, 0 deletions