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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2024-11-26 19:35:18 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-26 19:35:18 -0500 |
| commit | 065dc93d9626930b48f8e88b1e0a18c746951ce0 (patch) | |
| tree | 4b832a2f3b0a5a2d6a6f305dc621deedc4ffad03 /llvm/lib/Bitcode/Writer/BitcodeWriterPass.cpp | |
| parent | 991dcbc468763953f4b4e65fa3448e147cba5bba (diff) | |
| download | llvm-065dc93d9626930b48f8e88b1e0a18c746951ce0.zip llvm-065dc93d9626930b48f8e88b1e0a18c746951ce0.tar.gz llvm-065dc93d9626930b48f8e88b1e0a18c746951ce0.tar.bz2 | |
AMDGPU: Builtins & CodeGen support for v_cvt_scalef32_pk_{bf|f}16_{bf|fp}8 for gfx950 (#117793)
OPSEL[0] selects src_word to read.
Co-authored-by: Pravin Jagtap <Pravin.Jagtap@amd.com>
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriterPass.cpp')
0 files changed, 0 insertions, 0 deletions