diff options
| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-05 16:28:54 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-05 16:58:58 +0300 |
| commit | e2784c5d8cf6b2fe29d4b72addebadc619044c44 (patch) | |
| tree | c36693fa1ff13b84e259176c36ed4c827f544e19 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 3960693048a067e295d25c252b5f3a985c637bf2 (diff) | |
| download | llvm-e2784c5d8cf6b2fe29d4b72addebadc619044c44.zip llvm-e2784c5d8cf6b2fe29d4b72addebadc619044c44.tar.gz llvm-e2784c5d8cf6b2fe29d4b72addebadc619044c44.tar.bz2 | |
[X86][Costmodel] Load/store i64/f64 Stride=6 VF=4 interleaving costs
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/rc8jYxW6M - for intels `Block RThroughput: =18.0`; for ryzens, `Block RThroughput: =6.0`
So could pick cost of `18`.
For store we have:
https://godbolt.org/z/9PhPEr65G - for intels `Block RThroughput: =15.0`; for ryzens, `Block RThroughput: =6.0`
So we could pick cost of `15`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111093
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions