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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-05 16:28:49 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-05 16:58:58 +0300 |
| commit | 3960693048a067e295d25c252b5f3a985c637bf2 (patch) | |
| tree | 8eb9306f2cdad41a07e57b228f979a82d896f69d /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 79d6d12d9585dd584f259fa7395ad9465bef9aeb (diff) | |
| download | llvm-3960693048a067e295d25c252b5f3a985c637bf2.zip llvm-3960693048a067e295d25c252b5f3a985c637bf2.tar.gz llvm-3960693048a067e295d25c252b5f3a985c637bf2.tar.bz2 | |
[X86][Costmodel] Load/store i64/f64 Stride=6 VF=2 interleaving costs
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/onese7rec - for intels `Block RThroughput: =6.0`; for ryzens, `Block RThroughput: =3.0`
So could pick cost of `6`.
For store we have:
https://godbolt.org/z/bMd7dddnT - for intels `Block RThroughput: =8.0`; for ryzens, `Block RThroughput: <=6.0`
So we could pick cost of `8`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111092
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
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