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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-04 22:50:06 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-05 16:58:57 +0300 |
| commit | dcc2b0d9336c6d377cab4e2bcc7278a44123263d (patch) | |
| tree | d2866febb4f2dd0c93ec9921b72864ffba2ee131 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 7d91037fd2f71f1253bd8751a887eb4b6ed7d2ec (diff) | |
| download | llvm-dcc2b0d9336c6d377cab4e2bcc7278a44123263d.zip llvm-dcc2b0d9336c6d377cab4e2bcc7278a44123263d.tar.gz llvm-dcc2b0d9336c6d377cab4e2bcc7278a44123263d.tar.bz2 | |
[X86][Costmodel] Load/store i64/f64 Stride=4 VF=2 interleaving costs
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/z197317d1 - for intels `Block RThroughput: =6.0`; for ryzens, `Block RThroughput: =2.0`
So could pick cost of `6`.
For store we have:
https://godbolt.org/z/8dzszjf9q - for intels `Block RThroughput: =6.0`; for ryzens, `Block RThroughput: <=4.0`
So we could pick cost of `6`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111073
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
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