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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-04 19:30:14 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-05 16:58:57 +0300 |
| commit | 7d91037fd2f71f1253bd8751a887eb4b6ed7d2ec (patch) | |
| tree | 093c444c04a989050ed5612294e269e58033c329 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 4aee1e5b93e79ffd350485b866d4c6c982aab15f (diff) | |
| download | llvm-7d91037fd2f71f1253bd8751a887eb4b6ed7d2ec.zip llvm-7d91037fd2f71f1253bd8751a887eb4b6ed7d2ec.tar.gz llvm-7d91037fd2f71f1253bd8751a887eb4b6ed7d2ec.tar.bz2 | |
[X86][Costmodel] Load/store i32/f32 Stride=4 VF=16 interleaving costs
This one required quite a bit of assembly surgery, but the trend continues, so i think this is right.
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/EKWdj8cKT - for intels `Block RThroughput: <=32.0`; for ryzens, `Block RThroughput: <=24.0`
So could pick cost of `32`.
For store we have:
https://godbolt.org/z/zj4bb9P75 - for intels `Block RThroughput: =32.0`; for ryzens, `Block RThroughput: <=16.0`
So we could pick cost of `32`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111064
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
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