aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
diff options
context:
space:
mode:
authorRoman Lebedev <lebedev.ri@gmail.com>2021-10-05 16:27:58 +0300
committerRoman Lebedev <lebedev.ri@gmail.com>2021-10-05 16:58:57 +0300
commitd51532d8aad529fcefeedd686f0f1d2d967661f5 (patch)
treea7dcdf3899e2855056b6625b1837afecab2fe314 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
parent764fd5f463e4a2d13e77751e0da1c623d2781d4b (diff)
downloadllvm-d51532d8aad529fcefeedd686f0f1d2d967661f5.zip
llvm-d51532d8aad529fcefeedd686f0f1d2d967661f5.tar.gz
llvm-d51532d8aad529fcefeedd686f0f1d2d967661f5.tar.bz2
[X86][Costmodel] Load/store i32/f32 Stride=6 VF=4 interleaving costs
The only sched models that for cpu's that support avx2 but not avx512 are: haswell, broadwell, skylake, zen1-3 For load we have: https://godbolt.org/z/szEj1ceee - for intels `Block RThroughput: =15.0`; for ryzens, `Block RThroughput: <=8.8` So could pick cost of `15`. For store we have: https://godbolt.org/z/81bq4fTo1 - for intels `Block RThroughput: =12.0`; for ryzens, `Block RThroughput: <=10.0` So we could pick cost of `12`. I'm directly using the shuffling asm the llc produced, without any manual fixups that may be needed to ensure sequential execution. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D111087
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions