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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-05 16:27:53 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-05 16:58:57 +0300 |
| commit | 764fd5f463e4a2d13e77751e0da1c623d2781d4b (patch) | |
| tree | 4138515f53014311f35642d5fc5047f00496d72b /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | c800119c46fb266b7fc75409fd9cbbb1a6d8f72a (diff) | |
| download | llvm-764fd5f463e4a2d13e77751e0da1c623d2781d4b.zip llvm-764fd5f463e4a2d13e77751e0da1c623d2781d4b.tar.gz llvm-764fd5f463e4a2d13e77751e0da1c623d2781d4b.tar.bz2 | |
[X86][Costmodel] Load/store i32/f32 Stride=6 VF=2 interleaving costs
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/aec96Thee - for intels `Block RThroughput: =6.0`; for ryzens, `Block RThroughput: <=3.3`
So could pick cost of `6`.
For store we have:
https://godbolt.org/z/aec96Thee - for intels `Block RThroughput: =9.0`; for ryzens, `Block RThroughput: <=3.0`
So we could pick cost of `9`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111083
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
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