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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-04 22:50:11 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-05 16:58:57 +0300 |
| commit | c800119c46fb266b7fc75409fd9cbbb1a6d8f72a (patch) | |
| tree | 39758e88dc0cbff6bd2c0aeec8835b8dc63659d5 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 000ce0bfd52bbfe48732f378f5a67f307424552b (diff) | |
| download | llvm-c800119c46fb266b7fc75409fd9cbbb1a6d8f72a.zip llvm-c800119c46fb266b7fc75409fd9cbbb1a6d8f72a.tar.gz llvm-c800119c46fb266b7fc75409fd9cbbb1a6d8f72a.tar.bz2 | |
[X86][Costmodel] Load/store i64/f64 Stride=4 VF=8 interleaving costs
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/3M3hbq7n8 - for intels `Block RThroughput: =20.0`; for ryzens, `Block RThroughput: =8.0`
So could pick cost of `20`.
For store we have:
https://godbolt.org/z/zvnPYWTx7 - for intels `Block RThroughput: =20.0`; for ryzens, `Block RThroughput: =8.0`
So we could pick cost of `20`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111076
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
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