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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-04 22:50:11 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-05 16:58:57 +0300 |
| commit | 000ce0bfd52bbfe48732f378f5a67f307424552b (patch) | |
| tree | e97a5fa0ae953bccfbafa9308865fdff84c1b961 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | dcc2b0d9336c6d377cab4e2bcc7278a44123263d (diff) | |
| download | llvm-000ce0bfd52bbfe48732f378f5a67f307424552b.zip llvm-000ce0bfd52bbfe48732f378f5a67f307424552b.tar.gz llvm-000ce0bfd52bbfe48732f378f5a67f307424552b.tar.bz2 | |
[X86][Costmodel] Load/store i64/f64 Stride=4 VF=4 interleaving costs
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/MTKdzjvnr - for intels `Block RThroughput: =8.0`; for ryzens, `Block RThroughput: <=4.0`
So could pick cost of `8`.
For store we have:
https://godbolt.org/z/cMYEvqoah - for intels `Block RThroughput: =8.0`; for ryzens, `Block RThroughput: <=4.0`
So we could pick cost of `8`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111075
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
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