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| author | Jay Foad <jay.foad@amd.com> | 2019-12-20 15:13:57 +0000 |
|---|---|---|
| committer | Jay Foad <jay.foad@amd.com> | 2021-05-14 10:10:43 +0100 |
| commit | 7f81c5a5bae8329379b226d4efff6a44dfdeece9 (patch) | |
| tree | 586824fc6274f953960cc746bb45aa725578d1bb /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 10798709713a9b5d4ff8d8f5961b3c2fdb81d887 (diff) | |
| download | llvm-7f81c5a5bae8329379b226d4efff6a44dfdeece9.zip llvm-7f81c5a5bae8329379b226d4efff6a44dfdeece9.tar.gz llvm-7f81c5a5bae8329379b226d4efff6a44dfdeece9.tar.bz2 | |
[AMDGPU] getMemOperandsWithOffset: add vaddr operand for stack access BUF instructions
A consequence is that checkInstOffsetsDoNotOverlap can now distinguish
sp+offset from fp+offset, so it knows that it shouldn't try to work out
whether the accesses overlap just by comparing the offsets. For example
in these two instructions:
MIR:
BUFFER_STORE_DWORD_OFFSET %0:vgpr_32(s32), $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into stack + 4, addrspace 5)
%4:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN %stack.0.alloca, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 4 from `i8 addrspace(5)* undef`, addrspace 5)
ISA:
buffer_store_dword v0, off, s[0:3], s32 offset:4
buffer_load_dword v0, off, s[0:3], s34
Differential Revision: https://reviews.llvm.org/D73957
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions