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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-04 19:30:14 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-05 16:58:57 +0300 |
| commit | 4aee1e5b93e79ffd350485b866d4c6c982aab15f (patch) | |
| tree | 3424c809f9778d7962142a40f4fbbad3430be246 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 3c2e22b795485df28ca898bd3a58b6478c1e903d (diff) | |
| download | llvm-4aee1e5b93e79ffd350485b866d4c6c982aab15f.zip llvm-4aee1e5b93e79ffd350485b866d4c6c982aab15f.tar.gz llvm-4aee1e5b93e79ffd350485b866d4c6c982aab15f.tar.bz2 | |
[X86][Costmodel] Load/store i32/f32 Stride=4 VF=8 interleaving costs
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/a6rxMG6ec - for intels `Block RThroughput: =16.0`; for ryzens, `Block RThroughput: <=12.0`
So could pick cost of `16`.
For store we have:
https://godbolt.org/z/ced1bdqc9 - for intels `Block RThroughput: =16.0`; for ryzens, `Block RThroughput: <=8.0`
So we could pick cost of `16`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111063
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
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