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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-05 16:28:04 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-05 16:58:58 +0300 |
| commit | 79d6d12d9585dd584f259fa7395ad9465bef9aeb (patch) | |
| tree | 3e04037cd6db539df2d04a668c3cf1ce7690bdcb /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 2996a2b50fe39784b4c98748ba2a5b9595dc40f4 (diff) | |
| download | llvm-79d6d12d9585dd584f259fa7395ad9465bef9aeb.zip llvm-79d6d12d9585dd584f259fa7395ad9465bef9aeb.tar.gz llvm-79d6d12d9585dd584f259fa7395ad9465bef9aeb.tar.bz2 | |
[X86][Costmodel] Load/store i32/f32 Stride=6 VF=16 interleaving costs
This one required quite a bit of an assembly surgery, but i think it's in the right ballpark..
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/na97Kb96o - for intels `Block RThroughput: <=64.0`; for ryzens, `Block RThroughput: <=32.0`
So could pick cost of `64`.
For store we have:
https://godbolt.org/z/GG1WeoKar - for intels `Block RThroughput: =66.0`; for ryzens, `Block RThroughput: <=27.5`
So we could pick cost of `66`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111091
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
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