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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-05 16:28:03 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-05 16:58:57 +0300 |
| commit | 2996a2b50fe39784b4c98748ba2a5b9595dc40f4 (patch) | |
| tree | 7464c5e34cde0591e4293a7d3635dae053375c88 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | d51532d8aad529fcefeedd686f0f1d2d967661f5 (diff) | |
| download | llvm-2996a2b50fe39784b4c98748ba2a5b9595dc40f4.zip llvm-2996a2b50fe39784b4c98748ba2a5b9595dc40f4.tar.gz llvm-2996a2b50fe39784b4c98748ba2a5b9595dc40f4.tar.bz2 | |
[X86][Costmodel] Load/store i32/f32 Stride=6 VF=8 interleaving costs
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/jK85GWKaK - for intels `Block RThroughput: =31.0`; for ryzens, `Block RThroughput: <=17.0`
So could pick cost of `31`.
For store we have:
https://godbolt.org/z/hPWWhEEf9 - for intels `Block RThroughput: =33.0`; for ryzens, `Block RThroughput: <=13.8`
So we could pick cost of `33`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111089
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
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