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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-04 19:30:07 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-05 16:58:57 +0300 |
| commit | 3c2e22b795485df28ca898bd3a58b6478c1e903d (patch) | |
| tree | 0932ddf8b6952f035589b70bf0b544ff8dec3e38 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | b6234c1edffc8286815c61887eb02fd6ddab0090 (diff) | |
| download | llvm-3c2e22b795485df28ca898bd3a58b6478c1e903d.zip llvm-3c2e22b795485df28ca898bd3a58b6478c1e903d.tar.gz llvm-3c2e22b795485df28ca898bd3a58b6478c1e903d.tar.bz2 | |
[X86][Costmodel] Load/store i32/f32 Stride=4 VF=4 interleaving costs
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/avq1oz98W - for intels `Block RThroughput: =8.0`; for ryzens, `Block RThroughput: =4.0`
So could pick cost of `8`.
For store we have:
https://godbolt.org/z/89PGMc1qs - for intels `Block RThroughput: =6.0`; for ryzens, `Block RThroughput: <=6.0`
So we could pick cost of `6`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111061
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
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