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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-05 16:28:54 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-05 16:58:58 +0300 |
| commit | 3f9b235482a0e75946e3fc76dff93e0e29f104ab (patch) | |
| tree | bfdd069626a6691ec7c1e49a02301428a6561809 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | e2784c5d8cf6b2fe29d4b72addebadc619044c44 (diff) | |
| download | llvm-3f9b235482a0e75946e3fc76dff93e0e29f104ab.zip llvm-3f9b235482a0e75946e3fc76dff93e0e29f104ab.tar.gz llvm-3f9b235482a0e75946e3fc76dff93e0e29f104ab.tar.bz2 | |
[X86][Costmodel] Load/store i64/f64 Stride=6 VF=8 interleaving costs
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/1jfGddcre - for intels `Block RThroughput: =36.0`; for ryzens, `Block RThroughput: =12.0`
So could pick cost of `36`
For store we have:
https://godbolt.org/z/ao9srMT8r - for intels `Block RThroughput: =30.0`; for ryzens, `Block RThroughput: =12.0`
So we could pick cost of `30`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111094
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
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