diff options
| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-04 19:30:00 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-10-05 16:58:56 +0300 |
| commit | b6234c1edffc8286815c61887eb02fd6ddab0090 (patch) | |
| tree | 8c1afe10b4077dd6a3788ca47e800355b903c695 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 095c48fdf3d27a4f346f8680d1d7e89449bb557b (diff) | |
| download | llvm-b6234c1edffc8286815c61887eb02fd6ddab0090.zip llvm-b6234c1edffc8286815c61887eb02fd6ddab0090.tar.gz llvm-b6234c1edffc8286815c61887eb02fd6ddab0090.tar.bz2 | |
[X86][Costmodel] Load/store i32/f32 Stride=4 VF=2 interleaving costs
Finally, we are getting to the heavy-hitter stuff!
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/7crGWoar6 - for intels `Block RThroughput: =4.0`; for ryzens, `Block RThroughput: <=2.0`
So could pick cost of `4`.
For store we have:
https://godbolt.org/z/T8aq3MszM - for intels `Block RThroughput: =5.0`; for ryzens, `Block RThroughput: <=2.0`
So we could pick cost of `5`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111060
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions