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| author | Luís Marques <luismarques@lowrisc.org> | 2021-08-26 17:43:06 +0100 |
|---|---|---|
| committer | Luís Marques <luismarques@lowrisc.org> | 2021-08-26 17:43:43 +0100 |
| commit | 34e055d33e37cd87b9f6f4b0431a4c061628d036 (patch) | |
| tree | ebc25aafdec73f090e6013c8efa404355d4e2942 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 827dd17e262472a98982565406431454231b556d (diff) | |
| download | llvm-34e055d33e37cd87b9f6f4b0431a4c061628d036.zip llvm-34e055d33e37cd87b9f6f4b0431a4c061628d036.tar.gz llvm-34e055d33e37cd87b9f6f4b0431a4c061628d036.tar.bz2 | |
[Clang][RISCV] Implement getConstraintRegister for RISC-V
The getConstraintRegister method is used by semantic checking of inline
assembly statements in order to diagnose conflicts between clobber list
and input/output lists. By overriding getConstraintRegister we get those
diagnostics and we match RISC-V GCC's behavior. The implementation is
trivial due to the lack of single-register RISC-V-specific constraints.
Differential Revision: https://reviews.llvm.org/D108624
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions