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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2021-08-25 14:02:38 -0700 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2021-08-26 09:39:03 -0700 |
| commit | 827dd17e262472a98982565406431454231b556d (patch) | |
| tree | 620983b0381ac960092f4a681573de8140fbfc24 /llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | |
| parent | 8bb24289f3ac2bcf36d44d4951dc1a5e6822ae7b (diff) | |
| download | llvm-827dd17e262472a98982565406431454231b556d.zip llvm-827dd17e262472a98982565406431454231b556d.tar.gz llvm-827dd17e262472a98982565406431454231b556d.tar.bz2 | |
[AMDGPU] Invert partial vgpr to agpr spill lane order
On targets requiring VGPR alignment we may end up spilling an
unaligned register if we were partially spilled odd number of
leading lanes. The reminder will start with an odd register.
This problem is solved by inverting the order of lanes to
be spillied so that we start from the end.
Differential Revision: https://reviews.llvm.org/D108732
Diffstat (limited to 'llvm/lib/Bitcode/Writer/BitcodeWriter.cpp')
0 files changed, 0 insertions, 0 deletions