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| author | Florian Hahn <flo@fhahn.com> | 2024-01-25 18:28:44 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-01-25 18:28:44 +0000 |
| commit | eb678d89933684627ee2c5da47e53751f3fdbaa2 (patch) | |
| tree | adf67bde7b1e9331f494f9d152e1868f688b9683 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | c92ad411f2f94d8521cd18abcb37285f9a390ecb (diff) | |
| download | llvm-eb678d89933684627ee2c5da47e53751f3fdbaa2.zip llvm-eb678d89933684627ee2c5da47e53751f3fdbaa2.tar.gz llvm-eb678d89933684627ee2c5da47e53751f3fdbaa2.tar.bz2 | |
[AArch64] Combine store (trunc X to <3 x i8>) to sequence of ST1.b. (#78637)
Improve codegen for (trunc X to <3 x i8>) by converting it to a sequence
of 3 ST1.b, but first converting the truncate operand to either v8i8 or
v16i8, extracting the lanes for the truncate results and storing them.
At the moment, there are almost no cases in which such vector operations
will be generated automatically. The motivating case is non-power-of-2
SLP vectorization: https://github.com/llvm/llvm-project/pull/77790
PR: https://github.com/llvm/llvm-project/pull/78637
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions