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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2017-02-11 01:53:04 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2017-02-11 01:53:04 +0000 |
| commit | 8425f453ef77e3e1e14f804195802eae80261bef (patch) | |
| tree | 11e00ea3e045a8088d2541cecd66d6ee05f45cec /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | fc979dc9ddf6a29977381a606846c762457d41de (diff) | |
| download | llvm-8425f453ef77e3e1e14f804195802eae80261bef.zip llvm-8425f453ef77e3e1e14f804195802eae80261bef.tar.gz llvm-8425f453ef77e3e1e14f804195802eae80261bef.tar.bz2 | |
[ARM] Make f16 interleaved accesses expensive.
There are no vldN/vstN f16 variants, even with +fullfp16.
We could use the i16 variants, but, in practice, even with +fullfp16,
the f16 sequence leading to the i16 shuffle usually gets scalarized.
We'd need to improve our support for f16 codegen before getting there.
Teach the cost model to consider f16 interleaved operations as
expensive. Otherwise, we are all but guaranteed to end up with
a large block of scalarized vector code.
llvm-svn: 294819
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions