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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2017-02-11 01:53:00 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2017-02-11 01:53:00 +0000 |
| commit | fc979dc9ddf6a29977381a606846c762457d41de (patch) | |
| tree | 400850dc54959f271cc2ac98acae5128513fbaaf /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | f37fb89edcf21596acdc0d20925a394826ad1437 (diff) | |
| download | llvm-fc979dc9ddf6a29977381a606846c762457d41de.zip llvm-fc979dc9ddf6a29977381a606846c762457d41de.tar.gz llvm-fc979dc9ddf6a29977381a606846c762457d41de.tar.bz2 | |
[ARM] Don't lower f16 interleaved accesses.
There are no vldN/vstN f16 variants, even with +fullfp16.
We could use the i16 variants, but, in practice, even with +fullfp16,
the f16 sequence leading to the i16 shuffle usually gets scalarized.
We'd need to improve our support for f16 codegen before getting there.
Reject f16 interleaved accesses. If we try to emit the f16 intrinsics,
we'll just end up with a selection failure.
llvm-svn: 294818
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions