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| author | Craig Topper <craig.topper@intel.com> | 2020-05-14 10:35:29 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2020-05-14 10:58:00 -0700 |
| commit | 2fdeee9c8282df6e1fc0af02a503b4d2c908e49e (patch) | |
| tree | 6113abaaa372e484e8c01701e5d5977a0e1727bc /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 42a556050346ffaa0fe3c0cc4dab24ad65a115a4 (diff) | |
| download | llvm-2fdeee9c8282df6e1fc0af02a503b4d2c908e49e.zip llvm-2fdeee9c8282df6e1fc0af02a503b4d2c908e49e.tar.gz llvm-2fdeee9c8282df6e1fc0af02a503b4d2c908e49e.tar.bz2 | |
[X86] Add support for forming vXi16 PMULH instructions from shifts.
We already form PMULH when the shift is truncated. But we can
also do it from just a shift by extending the result.
Unfortunately, I get regressions if I try to replace the truncate
combine with this as we turn the truncate into a more complicated
sequence first. Then we are unable to combine that sequence with
the extend produced at the end of this combine.
Differential Revision: https://reviews.llvm.org/D79682
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions