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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-09-27 22:18:32 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-09-27 22:20:01 +0300 |
| commit | df2b42d12e4b4ff18bec8460c3d6ede6b411c048 (patch) | |
| tree | cbda5da045bd37bef9a1e4f6cff0bc14af80a80b /llvm/lib/Analysis/ModuleSummaryAnalysis.cpp | |
| parent | 45caac91c4e0caf64ec933f35c4a2d86a3fa31e3 (diff) | |
| download | llvm-df2b42d12e4b4ff18bec8460c3d6ede6b411c048.zip llvm-df2b42d12e4b4ff18bec8460c3d6ede6b411c048.tar.gz llvm-df2b42d12e4b4ff18bec8460c3d6ede6b411c048.tar.bz2 | |
[X86][Costmodel] Load/store i16 Stride=4 VF=4 interleaving costs
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/rnsf639Wh - for intels `Block RThroughput: =17.0`; for ryzens, `Block RThroughput: <=7.5`
So pick cost of `17`.
For store we have:
https://godbolt.org/z/565KKrcY6 - for intels `Block RThroughput: =6.0`; for ryzens, `Block RThroughput: =2.0`
So pick cost of `6`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D110537
Diffstat (limited to 'llvm/lib/Analysis/ModuleSummaryAnalysis.cpp')
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