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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-09-27 22:18:27 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-09-27 22:20:01 +0300 |
| commit | 45caac91c4e0caf64ec933f35c4a2d86a3fa31e3 (patch) | |
| tree | 8985a8b4840d007cf543b2c390552f91696809f2 /llvm/lib/Analysis/ModuleSummaryAnalysis.cpp | |
| parent | 18cf5b220d3f5e5ee1998a163764e15e56763815 (diff) | |
| download | llvm-45caac91c4e0caf64ec933f35c4a2d86a3fa31e3.zip llvm-45caac91c4e0caf64ec933f35c4a2d86a3fa31e3.tar.gz llvm-45caac91c4e0caf64ec933f35c4a2d86a3fa31e3.tar.bz2 | |
[X86][Costmodel] Load/store i16 Stride=4 VF=2 interleaving costs
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/5EYc6r9nh - for intels `Block RThroughput: =6.0`; for ryzens, `Block RThroughput: <=3.0`
So pick cost of `6`.
For store we have:
https://godbolt.org/z/z61e5d6GE - for intels `Block RThroughput: =2.0`; for ryzens, `Block RThroughput: <=1.0`
So pick cost of `2`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D110536
Diffstat (limited to 'llvm/lib/Analysis/ModuleSummaryAnalysis.cpp')
0 files changed, 0 insertions, 0 deletions