diff options
| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-09-27 22:18:36 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-09-27 22:20:01 +0300 |
| commit | 5615d6a6dd3f904cc9e1a219bfaf7df8183ee765 (patch) | |
| tree | 28c6f1d4ebab967a257a13ea1487572c71c25240 /llvm/lib/Analysis/ModuleSummaryAnalysis.cpp | |
| parent | df2b42d12e4b4ff18bec8460c3d6ede6b411c048 (diff) | |
| download | llvm-5615d6a6dd3f904cc9e1a219bfaf7df8183ee765.zip llvm-5615d6a6dd3f904cc9e1a219bfaf7df8183ee765.tar.gz llvm-5615d6a6dd3f904cc9e1a219bfaf7df8183ee765.tar.bz2 | |
[X86][Costmodel] Load/store i16 Stride=4 VF=8 interleaving costs
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/dd8T5P471 - for intels `Block RThroughput: =33.0`; for ryzens, `Block RThroughput: <=14.5`
So pick cost of `33`.
For store we have:
https://godbolt.org/z/zPxcKWhn4 - for intels `Block RThroughput: =10.0`; for ryzens, `Block RThroughput: <=6.0`
So pick cost of `10`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D110541
Diffstat (limited to 'llvm/lib/Analysis/ModuleSummaryAnalysis.cpp')
0 files changed, 0 insertions, 0 deletions