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author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-09-27 22:18:41 +0300 |
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committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-09-27 22:20:01 +0300 |
commit | 2a7a768dad3a77571fae8506d84078fe4ce3d105 (patch) | |
tree | 4993b0da3d8750646e602c0d25135eac3948cf5b /llvm/lib/Analysis/ModuleSummaryAnalysis.cpp | |
parent | ee5a050e2e548991f0369fa7ee29fb3e7aade071 (diff) | |
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[X86][Costmodel] Load/store i16 Stride=4 VF=32 interleaving costs
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For this tuple, measuring becomes problematic since there's a lot of spilling going on,
but apparently all these memory ops do not affect worst-case estimate at all here.
For load we have:
https://godbolt.org/z/zP4hd8MT6 - for intels `Block RThroughput: =150.0`; for ryzens, `Block RThroughput: <=59`
So pick cost of `150`.
For store we have:
https://godbolt.org/z/vKb8zTK8E - for intels `Block RThroughput: =32.0`; for ryzens, `Block RThroughput: <=24.0`
So pick cost of `64`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D110548
Diffstat (limited to 'llvm/lib/Analysis/ModuleSummaryAnalysis.cpp')
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