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| author | Craig Topper <craig.topper@intel.com> | 2020-05-14 10:06:07 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2020-05-14 10:31:28 -0700 |
| commit | 2b0b9b1148c205dfd73c70d195f51ef9895e2307 (patch) | |
| tree | 4fd7128220bdc22c318e2c6c7ecd97eb0d15c0bc /clang/lib/Basic/SourceManager.cpp | |
| parent | acb6f1ae096e8262fb30a267e9f40dea62432b26 (diff) | |
| download | llvm-2b0b9b1148c205dfd73c70d195f51ef9895e2307.zip llvm-2b0b9b1148c205dfd73c70d195f51ef9895e2307.tar.gz llvm-2b0b9b1148c205dfd73c70d195f51ef9895e2307.tar.bz2 | |
[X86] Fix a regression caused by moving combineLoopMAddPattern to IR
When I moved combineLoopMAddPattern to an IR pass. I didn't match the behavior of canReduceVMulWidth that was used in the SelectionDAG version. canReduceVMulWidth just calls computeSignBits and assumes a truncate is always profitable. The version I put in IR just looks for constants and zext/sext. Though I neglected to check the number of bits in input of the zext/sext.
This patch adds a check for the number of input bits to the sext/zext. And it adds a special case for add/sub with zext/sext inputs which can be handled by combineTruncatedArithmetic. Match the original SelectionDAG behavior appears to be a regression in some cases if the truncate isn't removed and becomes pack and permq. So enabling only this specific case is the conservative approach.
Differential Revision: https://reviews.llvm.org/D79909
Diffstat (limited to 'clang/lib/Basic/SourceManager.cpp')
0 files changed, 0 insertions, 0 deletions