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authorWilco Dijkstra <Wilco.Dijkstra@arm.com>2018-12-19 18:28:24 +0000
committerSzabolcs Nagy <szabolcs.nagy@arm.com>2019-01-09 10:35:34 +0000
commit02f440c1ef5d5d79552a524065aa3e2fabe469b9 (patch)
treeedffea1dbdd7ecb69885170e9b06fda564ebe7f7 /manual
parent69da3c9e87e0a692e79db0615a53782e4198dbf0 (diff)
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[AArch64] Add ifunc support for Ares
Add Ares to the midr_el0 list and support ifunc dispatch. Since Ares supports 2 128-bit loads/stores, use Neon registers for memcpy by selecting __memcpy_falkor by default (we should rename this to __memcpy_simd or similar). * manual/tunables.texi (glibc.cpu.name): Add ares tunable. * sysdeps/aarch64/multiarch/memcpy.c (__libc_memcpy): Use __memcpy_falkor for ares. * sysdeps/unix/sysv/linux/aarch64/cpu-features.h (IS_ARES): Add new define. * sysdeps/unix/sysv/linux/aarch64/cpu-features.c (cpu_list): Add ares cpu.
Diffstat (limited to 'manual')
-rw-r--r--manual/tunables.texi2
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/tunables.texi b/manual/tunables.texi
index 09a2565..af82082 100644
--- a/manual/tunables.texi
+++ b/manual/tunables.texi
@@ -360,7 +360,7 @@ This tunable is specific to powerpc, powerpc64 and powerpc64le.
The @code{glibc.cpu.name=xxx} tunable allows the user to tell @theglibc{} to
assume that the CPU is @code{xxx} where xxx may have one of these values:
@code{generic}, @code{falkor}, @code{thunderxt88}, @code{thunderx2t99},
-@code{thunderx2t99p1}.
+@code{thunderx2t99p1}, @code{ares}.
This tunable is specific to aarch64.
@end deftp