diff options
| author | Wilco Dijkstra <Wilco.Dijkstra@arm.com> | 2018-12-19 18:28:24 +0000 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2019-01-09 10:35:34 +0000 |
| commit | 02f440c1ef5d5d79552a524065aa3e2fabe469b9 (patch) | |
| tree | edffea1dbdd7ecb69885170e9b06fda564ebe7f7 | |
| parent | 69da3c9e87e0a692e79db0615a53782e4198dbf0 (diff) | |
| download | glibc-02f440c1ef5d5d79552a524065aa3e2fabe469b9.zip glibc-02f440c1ef5d5d79552a524065aa3e2fabe469b9.tar.gz glibc-02f440c1ef5d5d79552a524065aa3e2fabe469b9.tar.bz2 | |
[AArch64] Add ifunc support for Ares
Add Ares to the midr_el0 list and support ifunc dispatch. Since Ares
supports 2 128-bit loads/stores, use Neon registers for memcpy by
selecting __memcpy_falkor by default (we should rename this to
__memcpy_simd or similar).
* manual/tunables.texi (glibc.cpu.name): Add ares tunable.
* sysdeps/aarch64/multiarch/memcpy.c (__libc_memcpy): Use
__memcpy_falkor for ares.
* sysdeps/unix/sysv/linux/aarch64/cpu-features.h (IS_ARES):
Add new define.
* sysdeps/unix/sysv/linux/aarch64/cpu-features.c (cpu_list):
Add ares cpu.
| -rw-r--r-- | ChangeLog | 10 | ||||
| -rw-r--r-- | manual/tunables.texi | 2 | ||||
| -rw-r--r-- | sysdeps/aarch64/multiarch/memcpy.c | 2 | ||||
| -rw-r--r-- | sysdeps/unix/sysv/linux/aarch64/cpu-features.c | 1 | ||||
| -rw-r--r-- | sysdeps/unix/sysv/linux/aarch64/cpu-features.h | 2 |
5 files changed, 15 insertions, 2 deletions
@@ -1,3 +1,13 @@ +2019-01-09 Wilco Dijkstra <wdijkstr@arm.com> + + * manual/tunables.texi (glibc.cpu.name): Add ares tunable. + * sysdeps/aarch64/multiarch/memcpy.c (__libc_memcpy): Use + __memcpy_falkor for ares. + * sysdeps/unix/sysv/linux/aarch64/cpu-features.h (IS_ARES): + Add new define. + * sysdeps/unix/sysv/linux/aarch64/cpu-features.c (cpu_list): + Add ares cpu. + 2019-01-07 H.J. Lu <hongjiu.lu@intel.com> [BZ #24066] diff --git a/manual/tunables.texi b/manual/tunables.texi index 09a2565..af82082 100644 --- a/manual/tunables.texi +++ b/manual/tunables.texi @@ -360,7 +360,7 @@ This tunable is specific to powerpc, powerpc64 and powerpc64le. The @code{glibc.cpu.name=xxx} tunable allows the user to tell @theglibc{} to assume that the CPU is @code{xxx} where xxx may have one of these values: @code{generic}, @code{falkor}, @code{thunderxt88}, @code{thunderx2t99}, -@code{thunderx2t99p1}. +@code{thunderx2t99p1}, @code{ares}. This tunable is specific to aarch64. @end deftp diff --git a/sysdeps/aarch64/multiarch/memcpy.c b/sysdeps/aarch64/multiarch/memcpy.c index a27d571..f79f84c 100644 --- a/sysdeps/aarch64/multiarch/memcpy.c +++ b/sysdeps/aarch64/multiarch/memcpy.c @@ -36,7 +36,7 @@ extern __typeof (__redirect_memcpy) __memcpy_falkor attribute_hidden; libc_ifunc (__libc_memcpy, (IS_THUNDERX (midr) ? __memcpy_thunderx - : (IS_FALKOR (midr) || IS_PHECDA (midr) + : (IS_FALKOR (midr) || IS_PHECDA (midr) || IS_ARES (midr) ? __memcpy_falkor : (IS_THUNDERX2 (midr) || IS_THUNDERX2PA (midr) ? __memcpy_thunderx2 diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c index ce5998a..4243ced 100644 --- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c +++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c @@ -36,6 +36,7 @@ static struct cpu_list cpu_list[] = { {"thunderx2t99", 0x431F0AF0}, {"thunderx2t99p1", 0x420F5160}, {"phecda", 0x680F0000}, + {"ares", 0x411FD0C0}, {"generic", 0x0} }; diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.h b/sysdeps/unix/sysv/linux/aarch64/cpu-features.h index fa6d8db..6f8b35f 100644 --- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.h +++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.h @@ -51,6 +51,8 @@ #define IS_PHECDA(midr) (MIDR_IMPLEMENTOR(midr) == 'h' \ && MIDR_PARTNUM(midr) == 0x000) +#define IS_ARES(midr) (MIDR_IMPLEMENTOR(midr) == 'A' \ + && MIDR_PARTNUM(midr) == 0xd0c) struct cpu_features { |