aboutsummaryrefslogtreecommitdiff
path: root/sim
AgeCommit message (Expand)AuthorFilesLines
2012-04-09sim: bfin: new PINT modelMike Frysinger7-1/+386
2012-04-09sim: bfin: new GPIO modelMike Frysinger7-1/+352
2012-04-09sim: bfin: add shift astat testsMike Frysinger4-0/+777
2012-04-09sim: bfin: fix ASTAT issues in immediate shiftsMike Frysinger2-17/+64
2012-04-09sim: bfin: fix ASTAT/correctness issues with arithmetic shiftsMike Frysinger2-10/+67
2012-04-09sim: bfin: more astat testsMike Frysinger3-0/+397
2012-04-09sim: bfin: enable some parallel testsMike Frysinger5-4/+7
2012-04-09sim: bfin: more parallel insn checksMike Frysinger2-18/+84
2012-04-09sim: bfin: keep track of the exact position of parallel insnsMike Frysinger3-44/+75
2012-04-09sim: bfin: unify se_all helpers moreMike Frysinger7-54/+64
2012-04-08sim: bfin: drop excess space in negation insnMike Frysinger2-1/+5
2012-04-02sim: fix spelling typoMike Frysinger2-1/+5
2012-04-01sim: bfin: throw VEC_ILGAL_I with 32bit insn in group1/group2 slotsMike Frysinger2-0/+8
2012-04-01sim: bfin: simplify field width processing and fix build warningsMike Frysinger2-10/+6
2012-04-01sim: bfin: fix unused bfrom handling for BF535Mike Frysinger2-1/+5
2012-04-01sim: bfin: fix build warning/style with auxvt_sizeMike Frysinger2-2/+7
2012-03-31sim: bfin: fix typo in BF54x SIC initMike Frysinger2-1/+5
2012-03-31sim: bfin: include devices.h to fix build warningsMike Frysinger2-0/+5
2012-03-29Commit gdb and sim support for v850e2 and v850e2v3 on behalf ofKevin Buettner9-26/+3235
2012-03-27sim: add bugzilla markingMike Frysinger1-0/+1
2012-03-26sim: add a proper sim_core_trans_addr prototypeMike Frysinger4-1/+16
2012-03-25sim: bfin: skip .c/.S tests if no compiler is availableMike Frysinger2-0/+34
2012-03-25sim: bfin: disable redundant test that makes 32bit gas angryMike Frysinger2-1/+7
2012-03-25sim: bfin: fix typos in large constants in testsMike Frysinger6-5/+13
2012-03-24 * nrun.c: Add #ifdef HAVE_CONFIG_H and associated includes stanzaHans-Peter Nilsson2-0/+11
2012-03-24[PATCH] sim: make sure to include strsignal prototypeMike Frysinger104-3403/+6118
2012-03-24sim: testsuite: regen configure after rl78 additionMike Frysinger1-0/+4
2012-03-24sim: cris: update testsuite output after strsignal changeMike Frysinger25-24/+33
2012-03-23sim: testsuite: regen configure after rl78 additionMike Frysinger1-0/+3
2012-03-23sim: rx: fix warnings with AC_DEFINEMike Frysinger2-3/+8
2012-03-23sim: sync build_warnings handling with gdbMike Frysinger2-26/+44
2012-03-21sim: cris: update testsuite output after strsignal changeMike Frysinger38-37/+50
2012-03-21sim/testsuite/: split up arch-specific changelogsMike Frysinger7-613/+587
2012-03-19sim: bfin: add exhaustive parallel-insn testsMike Frysinger4-0/+33517
2012-03-19sim: bfin: unify se_all*opcodes testsMike Frysinger4-287/+255
2012-03-19sim: bfin: add tests for new shift behaviorMike Frysinger2-0/+11
2012-03-19sim: bfin: add tests for new shift behaviorMike Frysinger4-0/+137
2012-03-19sim: bfin: fix corner case Logical shift issuesMike Frysinger2-45/+64
2012-03-19sim: use character classes rather than rangesMike Frysinger4-18/+25
2012-03-19sim: nrun: decode signal when crashingMike Frysinger2-1/+6
2012-03-19sim: tests: ignore generated testsMike Frysinger2-0/+5
2012-03-19sim: bfin: ebiu_amc: push down hardcoded base addressesMike Frysinger2-2/+12
2012-03-19sim: bfin: import optimizations from 32bit test into 16bit testMike Frysinger2-35/+73
2012-03-19sim: bfin: use ARRAY_SIZEMike Frysinger2-1/+6
2012-03-14sim: ppc: fix compilation on AIX 7.1 due to st_pad name collisionsMike Frysinger2-0/+9
2012-03-04sim: bfin: drop old linux/mii.h workaroundsMike Frysinger5-23/+35
2012-03-03Update rx sim so that it'll print load statistics.Kevin Buettner7-5/+58
2012-02-16Update sim_fetch_register, sim_store_register for sh and mn10300.Kevin Buettner4-4/+15
2012-02-04Add support to GDB for the Renesas rl78 architecture.Kevin Buettner3-0/+579
2012-01-06sim: headers: use abs_srcdir to find helper scriptsMike Frysinger2-2/+9
generated by cgit v1.1 at 2024-07-12 00:32:06 +0000