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AgeCommit message (Expand)AuthorFilesLines
2023-01-10sim: modules: trigger generation from top-levelMike Frysinger1-0/+1
2023-01-02sim: build: move generated headers to built sourcesMike Frysinger1-0/+9
2023-01-01Update copyright year range in header of all files managed by GDBJoel Brobecker2-2/+2
2022-12-25sim: cpu: change default init to handle all cpusMike Frysinger1-1/+1
2022-12-25sim: v850: fix SMP compileMike Frysinger3-81/+84
2022-12-24sim: igen: drop move-if-changed usageMike Frysinger1-30/+15
2022-12-23sim: v850: standardize the arch-specific settings a littleMike Frysinger6-725/+733
2022-12-22sim: move bfd.h include out of sim-main.hMike Frysinger1-2/+0
2022-12-22sim: v850: switch from SIM_ADDR to address_wordMike Frysinger2-4/+4
2022-12-21sim: enable common sim_cpu usage everywhereMike Frysinger1-2/+0
2022-12-21sim: v850: invert sim_cpu storageMike Frysinger3-20/+23
2022-11-11sim: v850: rename v850.dc to align with other portsMike Frysinger2-1/+1
2022-11-07sim: v850: drop subdir configure logicMike Frysinger4-2955/+2
2022-11-05sim: run: move linking into top-levelMike Frysinger1-0/+8
2022-11-04sim: build: remove various obsolete generation dep variablesMike Frysinger1-4/+0
2022-11-03sim: v850: switch to standard (high-level) trace definesMike Frysinger3-6/+2
2022-11-02sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger1-4/+4
2022-10-31sim: reg: constify store helperMike Frysinger1-2/+2
2022-10-31sim: common: change sim_read & sim_write to use void* buffersMike Frysinger1-3/+3
2022-04-06Fix for v850e divq instructionJeff Law1-2/+2
2022-04-06Fix "bins" simulation for v850e3v5Jeff Law1-1/+8
2022-03-29Fix for MUL instruction on the v850Jeff Law1-2/+2
2022-02-21sim: gdbinit: hoist setup to common codeMike Frysinger1-9/+0
2022-01-06sim: v850: migrate to standard uintXX_t typesMike Frysinger5-111/+105
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker2-2/+2
2021-12-09sim: use ## for automake commentsMike Frysinger1-18/+18
2021-11-28sim: v850: switch to new target-newlib-syscallMike Frysinger3-67/+26
2021-11-15sim: split program path out of argv vectorMike Frysinger1-5/+1
2021-11-02sim: hoist mn10300 & v850 igen rules up to common buildsMike Frysinger2-67/+87
2021-10-31sim: v850: delete old gencode logicMike Frysinger1-7/+2
2021-10-31sim: igen: tighten up build outputMike Frysinger1-1/+1
2021-10-31sim: silence stamp touch rulesMike Frysinger1-1/+1
2021-10-31sim: standardize move-if-change rulesMike Frysinger1-15/+15
2021-10-31sim: mips/v850: remove redundant variable setupMike Frysinger1-2/+0
2021-08-17sim: rename ChangeLog files to ChangeLog-2021Mike Frysinger1-0/+0
2021-07-01sim: unify reserved instruction bits settingsMike Frysinger4-24/+6
2021-06-30sim: unify scache settingsMike Frysinger1-2/+0
2021-06-30sim: move default model to the runtime sim stateMike Frysinger2-2/+4
2021-06-22sim: drop configure scripts for simple portsMike Frysinger2-0/+11
2021-06-21sim: unify hardware settingsMike Frysinger3-49/+5
2021-06-21sim: hw: rework configure option & device selectionMike Frysinger2-37/+29
2021-06-20sim: delete SIM_AC_COMMON macroMike Frysinger4-5/+5
2021-06-20sim: unify general maintainer settingsMike Frysinger2-124/+0
2021-06-20sim: move sim-inline to the common codeMike Frysinger3-36/+5
2021-06-19sim: unify gettext/intl probing logicMike Frysinger2-85/+0
2021-06-19sim: unify toolchain dependency logicMike Frysinger2-1109/+1
2021-06-19sim: unify toolchain probing logicMike Frysinger2-1360/+26
2021-06-19sim: unify bfd library dependency testing logicMike Frysinger3-7691/+6
2021-06-19sim: unify various library testing logicMike Frysinger2-141/+6
2021-06-18sim: unify -Werror build settingsMike Frysinger3-112/+6
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