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path: root/sim/v850/simops.c
AgeCommit message (Expand)AuthorFilesLines
2022-12-25sim: v850: fix SMP compileMike Frysinger1-0/+3
2022-12-23sim: v850: standardize the arch-specific settings a littleMike Frysinger1-1/+1
2022-12-22sim: v850: switch from SIM_ADDR to address_wordMike Frysinger1-2/+2
2022-11-03sim: v850: switch to standard (high-level) trace definesMike Frysinger1-1/+1
2022-10-31sim: common: change sim_read & sim_write to use void* buffersMike Frysinger1-3/+3
2022-04-06Fix for v850e divq instructionJeff Law1-2/+2
2022-04-06Fix "bins" simulation for v850e3v5Jeff Law1-1/+8
2022-03-29Fix for MUL instruction on the v850Jeff Law1-2/+2
2022-01-06sim: v850: migrate to standard uintXX_t typesMike Frysinger1-26/+26
2021-11-28sim: v850: switch to new target-newlib-syscallMike Frysinger1-65/+23
2021-06-18sim: split sim-signal.h include outMike Frysinger1-0/+1
2021-06-08sim: v850: assume chown is availableMike Frysinger1-2/+0
2021-05-29sim: v850: add pointer casts for execv on WindowsMike Frysinger1-2/+2
2021-05-16sim: switch config.h usage to defs.hMike Frysinger1-0/+3
2021-01-31sim: v850: cleanup build warningsMike Frysinger1-0/+1
2021-01-31sim: v850: fix handling of SYS_timesMike Frysinger1-1/+1
2021-01-11sim: clean up C11 header includesMike Frysinger1-11/+0
2015-12-15Fix invalid left shift of negative valueDominik Vogt1-1/+1
2015-02-27Fixes problems building the V850 simulator introduced with the previous delta.Nick Clifton1-166/+172
2013-01-28 * simops.c (v850_rotl): New function.Nick Clifton1-0/+50
2012-03-29Commit gdb and sim support for v850e2 and v850e2v3 on behalf ofKevin Buettner1-1/+715
2011-03-21 * simops (OP_10007E0): Update errno handling as most trapsKevin Buettner1-3/+81
2011-02-14sim: punt zfree()Mike Frysinger1-8/+8
2008-02-06* simops.c (OP_1C007E0): Compensate for 64 bit hosts.DJ Delorie1-7/+9
2008-02-06Index: ChangeLogDJ Delorie1-82/+151
2004-01-18* simops.c: Include <sys/types.h>.Mark Kettenis1-0/+2
2003-04-06* simops.c (OP_40): Delete. Move code to...Nick Clifton1-44/+0
2002-11-302002-11-30 Andrew Cagney <cagney@redhat.com>Andrew Cagney1-19/+19
2002-09-30Fix handling of v850e bit-twiddle instructions.Jim Wilson1-2/+2
2002-09-27Fix bug in support for trap instruction.Jim Wilson1-1/+1
2002-08-29Makefile.in: Add gen-zero-r0 option.Nick Clifton1-1/+1
2002-06-17* simops.c (trace_result): Fix printf formatting.Andrew Cagney1-1/+2
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1-0/+2733
1999-04-16Initial creation of sourceware repositoryStan Shebs1-2778/+0
1997-09-19Clean up tracing for Bcond & jmp insns.Andrew Cagney1-240/+0
1997-09-19Fix cmov immed.Andrew Cagney1-17/+1
1997-09-19Fix cmov insn.Andrew Cagney1-16/+1
1997-09-17Clean up more tracing.Andrew Cagney1-35/+0
1997-09-17Fix tracing for: "ctret", "bsw", "hsw"Andrew Cagney1-103/+3
1997-09-16Smooth some of ALU tracing's rough edges.Andrew Cagney1-232/+127
1997-09-16Use trace_one_insn in trace functions. Buffer up trace data so thatAndrew Cagney1-163/+123
1997-09-16Restrict ldsr (load system register) to modifying just non-reserved PSW bits.Andrew Cagney1-35/+0
1997-09-16 * simops.c (Multiply64): Don't store into register zero.Jim Wilson1-2/+5
1997-09-15Fix sanitization for v850 V v850e V v850eqAndrew Cagney1-413/+198
1997-09-15For v850eq start up with US bit set.Andrew Cagney1-313/+117
1997-09-10Have trace_input, trace_output use sim-trace for IO.Andrew Cagney1-47/+57
1997-09-08Add multi-sim support to v850/v850e/v850eq simulators.Andrew Cagney1-103/+110
1997-09-04Replace memory model with one from sim/common directory.Andrew Cagney1-25/+115
1997-09-03Pacify gcc-current -Wall.Andrew Cagney1-0/+4
1997-09-03Add real SIM_DESC arg to v850 simulator.Andrew Cagney1-26/+34
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