| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2001-04-12 | * mips.igen (CFC1, CTC1): Pass the correct register numbers to | Jim Blandy | 1 | -1/+0 |
| 2001-02-24 | 2001-02-23 Ben Elliston <bje@redhat.com> | Ben Elliston | 1 | -0/+2 |
| 2001-02-19 | 2001-02-19 Ben Elliston <bje@redhat.com> | Ben Elliston | 1 | -1/+1 |
| 2000-10-19 | * cleanup | Frank Ch. Eigler | 1 | -5/+0 |
| 2000-05-29 | Define GPR_CLEAR | Nick Clifton | 1 | -0/+7 |
| 1999-04-16 | Initial creation of sourceware repositorygdb-4_18-branchpoint | Stan Shebs | 1 | -0/+785 |
| 1999-04-16 | Initial creation of sourceware repository | Stan Shebs | 1 | -1209/+0 |
| 1998-12-30 | * eCos->devo merge; tx3904 sanitize tags removed | Frank Ch. Eigler | 1 | -4/+30 |
| 1998-12-08 | * sky->devo merge, final part of sim merge | Frank Ch. Eigler | 1 | -27/+18 |
| 1998-11-23 | Switch mips-lsi-elf mips16 simulator to igen (from gencode). | Andrew Cagney | 1 | -2/+2 |
| 1998-11-12 | Add configury for mips-lsi-elf target (32 bit MIPS16). | Andrew Cagney | 1 | -4/+12 |
| 1998-10-27 | * MONSTER sky -> devo merge | Frank Ch. Eigler | 1 | -46/+134 |
| 1998-09-08 | * Patch for PR 17142, brought over from sky branch. | Frank Ch. Eigler | 1 | -6/+21 |
| 1998-07-31 | * sim-main.h: shadow NUM_CORE_REGS from tm-txvu.h | Ron Unrau | 1 | -6/+14 |
| 1998-06-29 | * interp.c (OPTION_BRANCH_BUG_4011): Add. | Gavin Romig-Koch | 1 | -1/+39 |
| 1998-06-16 | * sky-pke.c(read_pke_pc): return source address of current pc | Ron Unrau | 1 | -2/+15 |
| 1998-06-14 | * sky-engine.c: Set ordering of device issues to match enumerated type | Ron Unrau | 1 | -7/+7 |
| 1998-06-09 | * Handle 10 and 20-bit versions of Break instruction. Move handling | Ian Carmichael | 1 | -1/+19 |
| 1998-05-18 | * Monster patch - may destablize MIPS sims for a little while. | Frank Ch. Eigler | 1 | -7/+72 |
| 1998-05-07 | * sim-main.h (INSN_NAME): New arg `cpu'. | Doug Evans | 1 | -2/+8 |
| 1998-04-29 | * sim-main.h, sky-libvpe.c: r59fp_op* functions were called with | James Lemke | 1 | -11/+12 |
| 1998-04-22 | Move target specific stuff from sim/common/sim-base.h to sim/mips/sim-main.h | James Lemke | 1 | -0/+11 |
| 1998-04-21 | r5900.igen, sim-main.h, sky-libvpe.c: Add run-time option --float-type | James Lemke | 1 | -0/+19 |
| 1998-04-21 | Fix sanitize tag. The proper keyword is "start-sanitize-*", not | Jason Molenda | 1 | -2/+2 |
| 1998-04-21 | For new IGEN simulators, rewrite checks validating correct use of the | Andrew Cagney | 1 | -37/+47 |
| 1998-04-15 | Debug tx19 built from igen sources. | Andrew Cagney | 1 | -1/+7 |
| 1998-04-14 | Implement 32 bit MIPS16 instructions listed in m16.igen. | Andrew Cagney | 1 | -5/+7 |
| 1998-04-09 | * Backed out week-old attempt at enabling quadword memory access on | Frank Ch. Eigler | 1 | -12/+0 |
| 1998-04-09 | * Temporarily change LOADDRMASK in sky build. | Ian Carmichael | 1 | -0/+2 |
| 1998-04-07 | * R5900 COP2 is now ready for testing. Let loose the dogs! | Frank Ch. Eigler | 1 | -0/+11 |
| 1998-04-05 | * R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF | Frank Ch. Eigler | 1 | -2/+6 |
| 1998-04-05 | aclocal.m4: Don't enable inlining when cross-compiling. | Andrew Cagney | 1 | -9/+19 |
| 1998-04-02 | Re-do load/store operations so that they work for both 32 and 64 bit | Andrew Cagney | 1 | -2/+9 |
| 1998-04-01 | sky-vu.[ch]: prototype decls, cast floats to ints before register transfer | Ron Unrau | 1 | -3/+4 |
| 1998-03-30 | * Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide | Frank Ch. Eigler | 1 | -4/+7 |
| 1998-03-27 | * Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code | Frank Ch. Eigler | 1 | -1/+13 |
| 1998-03-03 | Fix DIV, DIV1 (wrong check for overflow) and DIVU1 (shouldn't check | Andrew Cagney | 1 | -1/+1 |
| 1998-02-28 | Add generic sim-info.c:sim_info() function using module mechanism. | Andrew Cagney | 1 | -1/+1 |
| 1998-02-25 | Finish implementation of r5900 instructions. | Andrew Cagney | 1 | -0/+16 |
| 1998-02-23 | sim-main.h: Re-arange r5900 registers so that they have their own | Andrew Cagney | 1 | -51/+96 |
| 1998-02-02 | Rewrite the mipsI/II/III pending-slot code. | Andrew Cagney | 1 | -36/+81 |
| 1998-02-01 | mips: Add multi-processor support for r5900. Others might work. | Andrew Cagney | 1 | -65/+74 |
| 1998-01-31 | igen: Fix SMP simulator generator support. | Andrew Cagney | 1 | -2/+4 |
| 1998-01-21 | Use macro GPR_SET(N,VAL) to clear zero registers. | Andrew Cagney | 1 | -2/+5 |
| 1997-11-20 | o Add SIM_SIGFPE to sim-signals | Andrew Cagney | 1 | -10/+0 |
| 1997-11-20 | Allow reads/writes to C0_CONFIG register. | Andrew Cagney | 1 | -1/+18 |
| 1997-11-11 | Fix IGEN version of MFC0, MTC0, SWC1, LWC1, SDC1, LDC1, LWXC1, | Andrew Cagney | 1 | -0/+3 |
| 1997-11-06 | Replace global IPC with function argument cia or current instruction | Andrew Cagney | 1 | -2/+0 |
| 1997-11-06 | IGEN likes to cache the current instruction address (CIA). Change the | Andrew Cagney | 1 | -49/+48 |
| 1997-11-05 | Rewrite the MIPS simulator's memory model so that it uses the generic | Andrew Cagney | 1 | -9/+13 |
