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| author | Andrew Cagney <cagney@redhat.com> | 1998-02-25 15:31:15 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1998-02-25 15:31:15 +0000 |
| commit | f89c0689a15c1c11f9128dc8985f548b9524d00e (patch) | |
| tree | 31fcdff8808b546d23a5a1e8172fdab98b0c8443 /sim/mips/sim-main.h | |
| parent | 6cd37f15638ba2742b672fa116c48c1c15187163 (diff) | |
| download | gdb-f89c0689a15c1c11f9128dc8985f548b9524d00e.zip gdb-f89c0689a15c1c11f9128dc8985f548b9524d00e.tar.gz gdb-f89c0689a15c1c11f9128dc8985f548b9524d00e.tar.bz2 | |
Finish implementation of r5900 instructions.
Diffstat (limited to 'sim/mips/sim-main.h')
| -rw-r--r-- | sim/mips/sim-main.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h index 457811a..5dd7071 100644 --- a/sim/mips/sim-main.h +++ b/sim/mips/sim-main.h @@ -188,6 +188,22 @@ convert (SD, CPU, cia, rm, op, from, to) /* start-sanitize-r5900 */ +/* Figure 10-5 FPU Control/Status Register. + Note: some of these bits are different to what is found in a + standard MIPS manual. */ +enum { + R5900_FCSR_C = BIT (23), /* OK */ + R5900_FCSR_I = BIT (17), + R5900_FCSR_D = BIT (16), + R5900_FCSR_O = BIT (15), + R5900_FCSR_U = BIT (14), + R5900_FCSR_CAUSE = MASK (16,14), + R5900_FCSR_SI = BIT (6), + R5900_FCSR_SD = BIT (5), + R5900_FCSR_SO = BIT (4), + R5900_FCSR_SU = BIT (3), +}; + typedef struct _sim_r5900_cpu { /* The R5900 has 32 x 128bit general purpose registers. |