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authorAndrew Cagney <cagney@redhat.com>1998-01-31 06:23:41 +0000
committerAndrew Cagney <cagney@redhat.com>1998-01-31 06:23:41 +0000
commit9ec6741b177fbd4d872a13002d540b60b11e4b78 (patch)
tree882348d86144658f9148f517f17c39dabe54df1e /sim/mips/sim-main.h
parent5266a484f4aa49a9ea52adbca949f6224ec2fcee (diff)
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igen: Fix SMP simulator generator support.
Use the bfd-processor name in the sim-engine switch. Add nr_cpus argument to sim_engine_run. tic80, v850, d30v, mips, common: Update mips: Fill in bfd-processor field of model records so that they match ../bfd/archures.
Diffstat (limited to 'sim/mips/sim-main.h')
-rw-r--r--sim/mips/sim-main.h6
1 files changed, 4 insertions, 2 deletions
diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h
index 201564b..1f56c78 100644
--- a/sim/mips/sim-main.h
+++ b/sim/mips/sim-main.h
@@ -289,7 +289,8 @@ struct _sim_cpu {
/* The following are internal simulator state variables: */
-#define CPU_CIA(CPU) (PC)
+#define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
+#define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
address_word dspc; /* delay-slot PC */
#define DSPC ((STATE_CPU (sd,0))->dspc)
@@ -378,7 +379,8 @@ struct _sim_cpu {
#define FGR (&REGISTERS[FGRIDX])
#define LO (REGISTERS[33])
#define HI (REGISTERS[34])
-#define PC (REGISTERS[37])
+#define PCIDX 37
+#define PC (REGISTERS[PCIDX])
#define CAUSE (REGISTERS[36])
#define SRIDX (32)
#define SR (REGISTERS[SRIDX]) /* CPU status register */