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2001-02-082001-02-08 Ben Elliston <bje@redhat.com>Chris Demetriou1-0/+5
* sim-main.c (load_memory): Pass cia to sim_core_read* functions. (store_memory): Likewise, pass cia to sim_core_write*.
2000-10-19* cleanupFrank Ch. Eigler1-0/+5
2000-10-19 Frank Ch. Eigler <fche@redhat.com> On advice from Chris G. Demetriou <cgd@sibyte.com>: * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
2000-07-27Don't clean *.igen.Andrew Cagney1-0/+5
2000-07-20* m16.igen (break): Call SignalException not sim_engine_halt.Andrew Cagney1-0/+4
2000-07-04Fix MOVN.fmt and MOVZ.fmt, need to test GPR[RT].Andrew Cagney1-0/+5
2000-06-23Fix printf arguments.Andrew Cagney1-0/+4
2000-05-29Define GPR_CLEARNick Clifton1-0/+8
2000-05-24Change profiling so that it is enabled by default. Re-generate everything.Andrew Cagney1-0/+4
2000-05-01* mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.Andrew Cagney1-0/+4
2000-04-09Fix printf botch.Andrew Cagney1-0/+4
2000-03-21* simplify eCos testingFrank Ch. Eigler1-0/+5
2000-03-21 Frank Ch. Eigler <fche@redhat.com> * interp.c (sim_open): Sort & extend dummy memory regions for --board=jmr3904 for eCos.
2000-03-02* autoconf correctionFrank Ch. Eigler1-0/+9
* merge from internal repo -> sourceware 2000-03-02 Frank Ch. Eigler <fche@redhat.com> * configure: Regenerated. Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com> * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf calls, conditional on the simulator being in verbose mode.
2000-02-05import gdb-2000-02-04 snapshotJason Molenda1-0/+5
1999-12-07import gdb-1999-12-06 snapshotJason Molenda1-0/+8
1999-11-17import gdb-1999-11-16 snapshotJason Molenda1-0/+5
1999-09-13import gdb-1999-09-13 snapshotJason Molenda1-0/+4
1999-09-09import gdb-1999-09-08 snapshotStan Shebs1-0/+16
1999-08-02import gdb-1999-08-02 snapshotJason Molenda1-0/+6
1999-07-19import gdb-1999-07-19 snapshotJason Molenda1-0/+15
1999-07-12import gdb-1999-07-12 snapshotJason Molenda1-0/+14
1999-07-07import gdb-1999-07-07 pre reformatJason Molenda1-0/+6
1999-05-11import gdb-1999-05-10Stan Shebs1-0/+4
1999-04-26import gdb-19990422 snapshotStan Shebs1-0/+21
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1-0/+2046
1999-04-16Initial creation of sourceware repositoryStan Shebs1-2873/+0
1999-02-05* Fix for PR 17794, brought over from ecc-98r1-branch.Frank Ch. Eigler1-3/+23
1999-02-05 Frank Ch. Eigler <fche@cygnus.com> * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the CPU, start periodic background I/O polls. (tx3904sio_poll): New function: periodic I/O poller.
1998-12-30* resolution of eCos-vs.-sky merge conflict!Frank Ch. Eigler1-0/+8
[ChangeLog] 1998-12-30 Frank Ch. Eigler <fche@cygnus.com> * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt. start-sanitize-sky * interp.c (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook. Call sim_engine_halt on BreakPoint. end-sanitize-sky [ChangeLog.sky] 1998-12-30 Frank Ch. Eigler <fche@cygnus.com> * sky-gdb.c (sky_sim_engine_halt): Do not set CIA here.
1998-12-30Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>Stan Shebs1-0/+5
* configure.in, configure (mips64vr5*-*-*): Added missing ;; in case statement. (actually a sanitize-cygnus mistake, but Rainer doesn't know that)
1998-12-30* eCos->devo merge; tx3904 sanitize tags removedFrank Ch. Eigler1-22/+18
1998-12-29 Frank Ch. Eigler <fche@cygnus.com> * interp.c (sim_open): Allocate jm3904 memory in smaller chunks. (load_word): Call SIM_CORE_SIGNAL hook on error. (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before starting. For exception dispatching, pass PC instead of NULL_CIA. (decode_coproc): Use COP0_BADVADDR to store faulting address. * sim-main.h (COP0_BADVADDR): Define. (SIM_CORE_SIGNAL): Define hook to call mips_core_signal. (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*(). (_sim_cpu): Add exc_* fields to store register value snapshots. * mips.igen (*): Replace memory-related SignalException* calls with references to SIM_CORE_SIGNAL hook. * dv-tx3904irc.c (tx3904irc_port_event): printf format warning fix. * sim-main.c (*): Minor warning cleanups.
1998-12-24m16.igen (DADDIU5): Correct type-o.Gavin Romig-Koch1-0/+26
1998-12-16New 'hack' generatorGavin Romig-Koch1-0/+30
1998-12-15missing *vr4320:Gavin Romig-Koch1-0/+6
1998-12-145xxx and elGavin Romig-Koch1-0/+5
1998-12-13for bfd:Gavin Romig-Koch1-0/+7
* archures.c,bfd-in2.h (bfd_mach_mips4121): New. * cpu-mips.c: Added vr4121. * elf32-mips.c (elf_mips_mach): Same. (_bfd_mips_elf_final_write_processing): Same. for gas: * config/tc-mips.c (mips_4121): New. (md_begin,mips_ip,md_longopts,md_parse_option): Add vr4121. for gcc: * config/mips/mips.c (override_options): Add vr4121. * config/mips/t-vr4xxx (MULTILIB_MATCHES): Same. for include/elf: * mips.h (E_MIPS_MACH_4121): New. for include/opcode: * mips.h (INSN_4121): New. for opcodes: * mips-dis.c (set_mips_isa_type): Add bfd_mach_mips4121. (_print_insn_mips): Same. * mips-opc.c: Add vr4121. for sim/mips: * configure.in,mips.igen,vr.igen: Add vr4121. * configure: Rebuilt.
1998-12-12 * configure.in (mips64vr4xxx): Enable TARGET_ENABLE_FR.Gavin Romig-Koch1-0/+12
Set mips_fpu, and mips_fpu_bitsize. Set sim_gen, and sim_igen_machine. * configure: Rebuild. * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts. * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1998-12-11Cleanups.Gavin Romig-Koch1-0/+4
1998-12-10* Fix for endianness bugs in tx39 sio sim.Frank Ch. Eigler1-0/+7
1998-12-10 Frank Ch. Eigler <fche@cygnus.com> * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes. (tx3904sio_tickle): fflush after a stdout character output.
1998-12-10Add missing sanitize markers.Jeff Law1-0/+10
1998-11-25Fix --enable-build-warnings=-Werror failures.Andrew Cagney1-0/+5
v850/simops.c, d10v/simops.c, v850/Makefile.in, d10v/Makefile.in: Include targ-vals.h instead of syscall.h. Replace SYS_* with TARGET_SYS_*. Add dependency. z8k/support.c: Include <errno.h> v850/simops.c: Replace long with portable signed32. mips/interp.c: Make sim_monitor global - needed by sky.
1998-11-25Explicitly tag vr41/mips16 instructions.Andrew Cagney1-0/+21
Update configure.in/configure.
1998-11-23Configure mips64vr4100-elf nee mips64vr41* as a 64 bit mips16 igen simulator.Andrew Cagney1-0/+10
Fix problems: All vr.igen instructions are 64 bit.
1998-11-23Pacify GCC.Andrew Cagney1-0/+5
1998-11-23Reconize target mips-tx19-elfAndrew Cagney1-0/+7
1998-11-23Switch mips-lsi-elf mips16 simulator to igen (from gencode).Andrew Cagney1-0/+12
1998-11-21* r5900.igen (CVT.W.S): Always round towards zero.Andrew Cagney1-0/+6
Update testsuite.
1998-11-12Add configury for mips-lsi-elf target (32 bit MIPS16).Andrew Cagney1-0/+26
Fix numerous problems with PENDING_* code. In old gencode simulator, don't double tick each cycle. Add BREAK instruction to MIPS16 gencode simulator.
1998-11-11div(-0) sets both I/SI and D/SD (PR16522)Andrew Cagney1-0/+4
1998-11-05* build fixFrank Ch. Eigler1-0/+4
Thu Nov 5 10:29:42 EST 1998 Frank Ch. Eigler <fche@cygnus.com> * r5900.igen (r59fp_opdiv): Correct erroneous FGR[FD] reference.
1998-11-05PR 16522Andrew Cagney1-0/+14
Fix RSQRT.S instruction, add test case.
1998-11-02* adding missing ChangeLog header lineFrank Ch. Eigler1-0/+1
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