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path: root/sim/ft32/interp.c
AgeCommit message (Expand)AuthorFilesLines
2021-06-18sim: split sim-signal.h include outMike Frysinger1-0/+1
2021-06-17sim: overhaul & unify endian settings managementMike Frysinger1-0/+1
2021-06-12sim: overhaul alignment settings managementMike Frysinger1-0/+3
2021-05-16sim: switch config.h usage to defs.hMike Frysinger1-1/+3
2021-05-14sim: create header namespaceMike Frysinger1-2/+2
2021-04-12sim: cgen: move cgen_cpu_max_extra_bytes logic into the common codeMike Frysinger1-1/+1
2021-01-01Update copyright year range in all GDB filesJoel Brobecker1-1/+1
2020-01-01Update copyright year range in all GDB files.Joel Brobecker1-1/+1
2019-01-01Update copyright year range in all GDB files.Joel Brobecker1-1/+1
2018-01-02Update copyright year range in all GDB filesJoel Brobecker1-1/+1
2017-11-01FT32: support for FT32B processor - part 2/2James Bowman1-7/+15
2017-10-12FT32: support for FT32B processor - part 1James Bowman1-7/+11
2017-01-01update copyright year range in GDB filesJoel Brobecker1-1/+1
2016-01-06sim: sim_{create_inferior,open,parse_args}: constify argv/env slightlyMike Frysinger1-3/+3
2016-01-03sim: parse_args: display getopt error ourselvesMike Frysinger1-3/+1
2016-01-01GDB copyright headers update after running GDB's copyright.py script.Joel Brobecker1-1/+1
2015-12-26sim: standardize sim_create_inferior handling of argv a bit moreMike Frysinger1-1/+5
2015-11-15sim: sim-close: unify sim_close logicMike Frysinger1-6/+0
2015-09-29sim: ft32: correct simulation of MEMCPY and MEMSETJames Bowman1-2/+2
2015-09-29sim: ft32: correctly simulate PM write portJames Bowman1-2/+6
2015-09-22sim: ft32: add character input portJames Bowman1-0/+2
2015-04-17sim: replace CIA_{GET,SET} with CPU_PC_{GET,SET}Mike Frysinger1-3/+3
2015-04-13sim: ft32: fix ft32_pc_get logicMike Frysinger1-1/+1
2015-04-12sim: ft32: delete sim_read/sim_write funcsMike Frysinger1-22/+0
2015-03-28sim: ft32: new portJames Bowman1-0/+913
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