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path: root/sim/d10v/interp.c
AgeCommit message (Expand)AuthorFilesLines
2021-01-11sim: clean up C11 header includesMike Frysinger1-9/+0
2021-01-09sim: cr16/d10v: move storage out of headerMike Frysinger1-0/+2
2016-01-06sim: sim_{create_inferior,open,parse_args}: constify argv/env slightlyMike Frysinger1-2/+4
2016-01-03sim: parse_args: display getopt error ourselvesMike Frysinger1-3/+1
2015-12-30sim: arm/d10v/h8300/m68hc11/microblaze/mips/mn10300/moxie/sh/v850: convert to...Mike Frysinger1-6/+11
2015-11-15sim: cr16/d10v: drop redundant call to sim_create_inferiorMike Frysinger1-1/+0
2015-11-15sim: d10v: drop global callback stateMike Frysinger1-63/+59
2015-11-15sim: d10v: convert to common sim engine logicMike Frysinger1-118/+59
2015-11-15sim: d10v: push down sd/cpu varsMike Frysinger1-82/+101
2015-11-15sim: sim-close: unify sim_close logicMike Frysinger1-7/+0
2015-11-10sim: cr16/d10v: localize translation funcsMike Frysinger1-3/+3
2015-04-17sim: arm/cr16/d10v/h8300/microblaze/sh: fill out sim-cpu pc fetch/store helpersMike Frysinger1-0/+22
2015-04-02sim: d10v: fix signal updatesMike Frysinger1-8/+5
2015-04-01sim: run: punt!Mike Frysinger1-2/+0
2015-03-30sim: d10v: convert to nrunMike Frysinger1-115/+68
2015-03-30sim: d10v: delete NEED_UI_LOOP_HOOK handlingMike Frysinger1-19/+0
2015-03-30sim: d10v: clean up misc warningsMike Frysinger1-81/+27
2015-03-30sim: d10v: use common configure optionsMike Frysinger1-0/+8
2014-03-10sim: constify arg to sim_do_commandMike Frysinger1-1/+1
2014-03-05sim: constify prog_nameMike Frysinger1-1/+1
2014-01-07remove PARAMS from simTom Tromey1-10/+10
2012-06-19include "config.h" instead of BFD's sysdep.h in d10v/interp.cJoel Brobecker1-1/+13
2012-05-24gdb/Pedro Alves1-2/+2
2010-04-14sim: constify sim_write source buffer (part 2)Mike Frysinger1-1/+1
2006-04-18* interp.c (sim_stop_reason): Fix typo.Nick Clifton1-1/+1
2005-11-28 * remote-sim.c (gdbsim_wait): Pass target signal numbers toMark Mitchell1-6/+3
2004-06-29Index: mn10200/ChangeLogAndrew Cagney1-3/+3
2003-06-222003-06-22 Andrew Cagney <cagney@redhat.com>Andrew Cagney1-36/+26
2003-05-07Index: gdb/ChangeLogAndrew Cagney1-18/+24
2003-02-27Index: arm/ChangeLogAndrew Cagney1-2/+2
2002-06-15Fix for transfers across segments.Tom Rix1-2/+3
2002-06-09Move include/callback.h and include/remote-sim.h to include/gdb/.Andrew Cagney1-2/+2
2002-06-08Fix name of enum used in cast (sim_fetch_register, sim_store_register).Andrew Cagney1-2/+2
2002-06-01Fill-out d10v enum so that there are no ``=''.Andrew Cagney1-56/+112
2002-05-282002-05-28 Elena Zannoni <ezannoni@redhat.com>Elena Zannoni1-0/+8
2002-05-24* sim-d10v.h: Delete file. Moved to include/gdb/.Andrew Cagney1-1/+1
2001-08-02Removed a section of code that didn't do anything, but left values inJohn R. Moore1-19/+0
2000-05-03Add missing ChangeLog.Andrew Cagney1-1/+2
2000-04-18Add support for SIGILL (reserved-instruction-exception).Andrew Cagney1-2/+7
2000-02-22When SIM_HAVE_ENVIRONMENT: use sim_set_trace() to enable tracingAndrew Cagney1-10/+2
2000-02-09Report SIGBUS and halt simulation when ld/st detect a misaligned address.Andrew Cagney1-2/+35
2000-01-06import gdb-2000-01-05 snapshotJason Molenda1-0/+1
1999-11-17import gdb-1999-11-16 snapshotJason Molenda1-288/+557
1999-09-13import gdb-1999-09-13 snapshotJason Molenda1-20/+75
1999-04-26import gdb-19990422 snapshotStan Shebs1-0/+18
1999-04-16Initial creation of sourceware repositorygdb-4_18-branchpointStan Shebs1-0/+1086
1999-04-16Initial creation of sourceware repositoryStan Shebs1-1069/+0
1998-02-16Implement "dbt" and "rtd" instructions.Andrew Cagney1-15/+25
1998-02-10D10v memory map changed. Update.Andrew Cagney1-136/+173
1998-01-22 * interp.c (UMEM_SEGMENTS): New define, set to 128.Fred Fish1-54/+120
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