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| author | Andrew Cagney <cagney@redhat.com> | 2000-02-09 05:08:42 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 2000-02-09 05:08:42 +0000 |
| commit | 7fc5b5adca549dda57f47043626d22c3f1e94430 (patch) | |
| tree | cdef0374ca62b628a043bf132ec07913b53edb2d /sim/d10v/interp.c | |
| parent | 489137c0360f94c18f650b810f1129569f3b3d70 (diff) | |
| download | gdb-7fc5b5adca549dda57f47043626d22c3f1e94430.zip gdb-7fc5b5adca549dda57f47043626d22c3f1e94430.tar.gz gdb-7fc5b5adca549dda57f47043626d22c3f1e94430.tar.bz2 | |
Report SIGBUS and halt simulation when ld/st detect a misaligned address.
Diffstat (limited to 'sim/d10v/interp.c')
| -rw-r--r-- | sim/d10v/interp.c | 37 |
1 files changed, 35 insertions, 2 deletions
diff --git a/sim/d10v/interp.c b/sim/d10v/interp.c index 33b5dca..80898ab 100644 --- a/sim/d10v/interp.c +++ b/sim/d10v/interp.c @@ -965,6 +965,25 @@ sim_resume (sd, step, siggnal) if (step) sim_stop (sd); + switch (siggnal) + { + case 0: + break; +#ifdef SIGBUS + case SIGBUS: +#endif + case SIGSEGV: + SET_BPC (PC); + SET_BPSW (PSW); + SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT))); + JMP (AE_VECTOR_START); + SLOT_FLUSH (); + break; + default: + /* just ignore it */ + break; + } + do { iaddr = imem_addr ((uint32)PC << 2); @@ -1057,11 +1076,16 @@ int sim_trace (sd) SIM_DESC sd; { + enum sim_stop reason; + static int sigrc = 0; #ifdef DEBUG d10v_debug = DEBUG; #endif - sim_resume (sd, 0, 0); - return 1; + /* NOTE: SIGRC starts with zero and is then, always the value + returned by the last sim_stop_reason() call. */ + sim_resume (sd, 0, sigrc); + sim_stop_reason (sd, &reason, &sigrc); + return (reason != sim_stopped || sigrc != SIGINT); } void @@ -1267,6 +1291,15 @@ sim_stop_reason (sd, reason, sigrc) *sigrc = GPR (0); break; + case SIG_D10V_BUS: + *reason = sim_stopped; +#ifdef SIGBUS + *sigrc = SIGBUS; +#else + *sigrc = SIGSEGV; +#endif + break; + default: /* some signal */ *reason = sim_stopped; if (stop_simulator && !State.exception) |