aboutsummaryrefslogtreecommitdiff
path: root/sim/common
AgeCommit message (Expand)AuthorFilesLines
2021-02-21sim: common: split up acinclude.m4 into individual m4 filesMike Frysinger2-875/+4
2021-02-13sim: switch to AC_CONFIG_MACRO_DIRSMike Frysinger2-14/+4
2021-02-13sim: common: delete unused aclocal.m4Mike Frysinger2-15/+4
2021-02-06sim: watchpoints: use common sim_pc_getMike Frysinger5-10/+87
2021-02-06sim: add ChangeLog entries for last commitsMike Frysinger1-0/+5
2021-02-06sim: common: switch AC_CONFIG_HEADERSMike Frysinger1-2/+1
2021-02-06sim: drop use of bfd/configure.hostMike Frysinger3-8/+8
2021-02-04sim: riscv: new portMike Frysinger3-0/+56
2021-01-31sim: cgen-trace: tweak printf callMike Frysinger2-1/+5
2021-01-31sim: cgen-accfp: Fix pointer sign warningsStafford Horne2-3/+9
2021-01-30sim: common: change gennltvals helper to PythonMike Frysinger4-239/+238
2021-01-30sim: watchpoints: change sizeof_pc to sizeof(sim_cia)Mike Frysinger3-4/+9
2021-01-30sim: profile: fix bucketing with 64-bit targetsMike Frysinger2-2/+6
2021-01-30sim: hw: replace fgets with getlineMike Frysinger2-30/+41
2021-01-30sim: common: sort nltvals.defMike Frysinger3-90/+95
2021-01-18sim: common: simplify version scriptMike Frysinger3-13/+15
2021-01-18sim: common: delete configure & MakefileMike Frysinger4-3887/+4
2021-01-18sim: common: modernize gennltvals.shMike Frysinger4-167/+237
2021-01-13sim: watch: add basic default handler that trapsMike Frysinger2-1/+18
2021-01-13sim: watch: fix range expression processingMike Frysinger2-1/+5
2021-01-13sim: watch: fix pc watchpoints on little endian host systemsMike Frysinger4-5/+14
2021-01-12sim: common: use #error properlyMike Frysinger2-1/+5
2021-01-11sim: always call SIM_AC_OPTION_WARNINGSMike Frysinger2-1/+7
2021-01-11sim: common: fix printf formatsMike Frysinger2-1/+6
2021-01-11sim: clean up C11 header includesMike Frysinger28-187/+16
2021-01-09sim: common: clean up asprintf includes a bitMike Frysinger4-5/+7
2021-01-09sim: clean up stale AC_PREREQ refsMike Frysinger2-12/+5
2021-01-09sim: enable -Werror by default for some archesMike Frysinger2-5/+11
2021-01-09sim: hw: rework code to avoid gcc warningsMike Frysinger2-7/+8
2021-01-09sim: common: add missing stdlib.h for abort()Mike Frysinger5-0/+9
2021-01-08sim: require a C11 compilerMike Frysinger3-1/+34
2021-01-07gdb/sim: add support for exporting memory mapMike Frysinger2-0/+61
2021-01-04sim: update bug URI to https://Mike Frysinger2-1/+6
2021-01-04sim: common: version: add build & homepage info when interactiveMike Frysinger2-0/+20
2021-01-04sim: common: use sim_config_print nameMike Frysinger3-3/+3
2021-01-04sim: common: add a version output helper w/copyright+license infoMike Frysinger3-1/+31
2021-01-04sim: common: rename sim_print_configMike Frysinger3-2/+8
2021-01-02sim: common: add align_{up,down} to match gdbMike Frysinger2-13/+10
2021-01-01Update copyright year range in all GDB filesJoel Brobecker114-114/+114
2020-08-10[sim] Fix mbuild build breaker in sim-cpu.cTom de Vries2-0/+6
2020-01-19sim: add some stdlib.h includesSimon Marchi7-2/+21
2020-01-01Update copyright year range in all GDB files.Joel Brobecker114-114/+114
2019-12-19Add install-strip to sim/Tom Tromey2-0/+6
2019-12-04sim-utils.c: prevent buffer overflow.Pavel I. Kryukov2-4/+8
2019-09-23sim: Add PRU simulator portDimitar Dimitrov3-0/+40
2019-09-19bfd_section_* macrosAlan Modra2-7/+7
2019-06-13sim/common: wire up new unordered comparisonsStafford Horne3-0/+33
2019-06-13sim/common: Wire in df/di conversionStafford Horne2-0/+29
2019-04-13sim: Use host not target byte order for merging and splitting valuesAndrew Burgess2-5/+14
2019-03-28sim: fix all sim buildsAndrew Burgess3-0/+8