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| author | Mike Frysinger <vapier@gentoo.org> | 2015-03-23 00:30:52 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2021-01-30 10:14:21 -0500 |
| commit | d4e3adda1225d29b99f7bc81cc711806ecaacb70 (patch) | |
| tree | 9e28132b4b36b74d943160bfb5aa7dd03e19b494 /sim/common | |
| parent | 18d4b488f4538f11cfdc618ddfb26eaf2c955fb7 (diff) | |
| download | gdb-d4e3adda1225d29b99f7bc81cc711806ecaacb70.zip gdb-d4e3adda1225d29b99f7bc81cc711806ecaacb70.tar.gz gdb-d4e3adda1225d29b99f7bc81cc711806ecaacb70.tar.bz2 | |
sim: watchpoints: change sizeof_pc to sizeof(sim_cia)
Existing ports already have sizeof_pc set to the same size as sim_cia,
so simply make that part of the core code. We already assume this in
places by way of sim_pc_{get,set}, and this is how it's documented in
the sim-base.h API.
There is code to allow sims to pick different register word sizes from
address sizes, but most ports use the defaults for both (32-bits), and
the few that support multiple register sizes never change the address
size (so address defaults to register). I can't think of any machine
where the register hardware size would be larger than the address word
size either. We have ABIs that behave that way (e.g. x32), but the
hardware is still equivalent register sized.
Diffstat (limited to 'sim/common')
| -rw-r--r-- | sim/common/ChangeLog | 6 | ||||
| -rw-r--r-- | sim/common/sim-watch.c | 6 | ||||
| -rw-r--r-- | sim/common/sim-watch.h | 1 |
3 files changed, 9 insertions, 4 deletions
diff --git a/sim/common/ChangeLog b/sim/common/ChangeLog index dbf030d..c7d6439 100644 --- a/sim/common/ChangeLog +++ b/sim/common/ChangeLog @@ -1,5 +1,11 @@ 2021-01-30 Mike Frysinger <vapier@gentoo.org> + * sim-watch.c (schedule_watchpoint): Change sizeof_pc to sizeof + sim_cia. + * sim-watch.h (struct _sim_watchpoints): Delete sizeof_pc. + +2021-01-30 Mike Frysinger <vapier@gentoo.org> + * sim-profile.c (profile_pc_init): Change 1 in shifts to 1ULL. 2021-01-30 Mike Frysinger <vapier@gentoo.org> diff --git a/sim/common/sim-watch.c b/sim/common/sim-watch.c index 6d17729..9ccd472 100644 --- a/sim/common/sim-watch.c +++ b/sim/common/sim-watch.c @@ -172,7 +172,7 @@ schedule_watchpoint (SIM_DESC sd, case pc_watchpoint: point->event = sim_events_watch_sim (sd, watch->pc, - watch->sizeof_pc, + sizeof (sim_cia), HOST_BYTE_ORDER, point->is_within, point->arg0, point->arg1, @@ -377,8 +377,8 @@ static const OPTION watchpoint_options[] = static const char *default_interrupt_names[] = { "int", 0, }; /* This default handler is "good enough" for targets that just want to trap into - gdb when watchpoints are hit, and have only configured STATE_WATCHPOINTS pc & - sizeof_pc fields. */ + gdb when watchpoints are hit, and have only configured the STATE_WATCHPOINTS + pc field. */ static void default_interrupt_handler (SIM_DESC sd, void *data) { diff --git a/sim/common/sim-watch.h b/sim/common/sim-watch.h index 1fd66fc..52a8d12 100644 --- a/sim/common/sim-watch.h +++ b/sim/common/sim-watch.h @@ -50,7 +50,6 @@ typedef struct _sim_watchpoints { /* FIXME: In the future this shall be generalized so that any of the N processors M registers can be watched */ void *pc; - int sizeof_pc; /* Pointer to the handler for interrupt watchpoints */ /* FIXME: can this be done better? */ |