aboutsummaryrefslogtreecommitdiff
path: root/sim/arm
AgeCommit message (Collapse)AuthorFilesLines
2001-03-06Fix BLX(1) for ThumbNick Clifton2-5/+24
2001-02-28Add support for disabling alignment checks when performing GDB interfaceNick Clifton8-44/+95
calls or SWI emulaiton routines. (Alignment checking code has not yet been contributed).
2001-02-16Remove Prefetch abort for breakpoints. Instead set the state to RESUME.Nick Clifton2-12/+7
2001-02-15Add code to preserve processor mode when a prefetchNick Clifton2-0/+14
abort is signalled after processing a breakpoint.
2001-02-14Reset processor into ARM mode for any machine type except the early ARMs.Nick Clifton2-12/+20
2001-02-14remove spurious whitespaceNick Clifton1-6/+6
2001-02-14Prevent Aborts from happening whilst emulating a SWINick Clifton2-62/+83
2001-02-12Fix definition of NEGBRANCHNick Clifton2-1/+6
2001-02-01Add parentheses ready for future conbtributionNick Clifton1-39/+63
2001-02-01Update base address register after restoring register bank.Nick Clifton2-26/+64
2001-02-01Detect installation of SWI vector by running program as well as loading program.Nick Clifton5-7/+18
2000-12-19Fix test for StoreDouble Instruction.Nick Clifton2-12/+17
2000-12-11Add 0x91 as an FPE SWI.Nick Clifton2-0/+5
2000-12-08oops - remove redundant prototype introduced in previous deltaNick Clifton1-2/+0
2000-12-08Add emulation of double word load and store instructions.Nick Clifton2-3/+348
2000-12-03Suppress support of DEMON swi's in XScale mode.Nick Clifton2-71/+109
2000-11-30Add support for ARM's v5TE architecture and Intel's XScale extenstionsNick Clifton10-250/+1763
2000-09-15Replace StrongARM property with v4 and v5 properties.Nick Clifton6-90/+119
2000-08-15Compute write back value for post increment loads beforeNick Clifton2-34/+47
performing the load in case the offset register is overwritten.
2000-07-142000-07-14 Fernando Nasser <fnasser@cygnus.com>Fernando Nasser2-1/+5
* wrapper.c (sim_create_inferior): Fix typo in the previous patch.
2000-07-142000-07-14 Fernando Nasser <fnasser@cygnus.com>Fernando Nasser2-0/+9
* wrapper.c (sim_create_inferior): Reset mode to ARM when creating a new inferior.
2000-07-04* armvirt.c (ABORTS): Do not define.Alexandre Oliva2-1/+3
2000-07-04* armdefs.h (struct ARMul_State): Add is_StrongARM.Alexandre Oliva5-11/+59
(ARM_Strong_Prop, STRONGARM): Define. * arminit.c (ARMul_NewState): Reset is_StrongARM. (ARMul_SelectProcessor): Set is_StrongARM. * wrapper.c (sim_create_inferior): Use bfd machine type to determine processor type to emulate. * armemu.h (BUSUSEDINCPCS, BUSUSEDINCPCN): Don't increment PC when emulating StrongARM.
2000-07-04* armemu.c (ARMul_Emulate, t_undefined): Proceed to next insn.Alexandre Oliva2-1/+3
2000-07-04* armemu.h (INSN_SIZE): New macro.Alexandre Oliva4-45/+48
(SET_ABORT): Save CPSR in SPSR and set LR. * armemu.c (ARMul_Emulate, isize): Set to INSN_SIZE. (WriteR15, WriteSR15): Do not discard bit 1 in Thumb mode. * arminit.c (ARMul_Abort): Use new SETABORT and INSN_SIZE.
2000-07-04* armemu.c (LoadSMult): Use WriteR15() to discard the leastAlexandre Oliva2-2/+5
significant bits of PC.
2000-07-04* armemu.h (WRITEDESTB): New macro.Alexandre Oliva3-37/+48
* armemu.c (ARMul_Emulate26, bl): Use WriteR15Branch() to modify PC. Moved the existing logic... (WriteR15Branch): ... here. New function. (WriteR15, WriteSR15): Drop the two least significant bits. (LoadSMult): Use WriteR15Branch() to modify PC. (LoadMult): Use WRITEDESTB() instead of WRITEDEST().
2000-07-04* armemu.h (GETSPSR): Call ARMul_GetSPSR().Alexandre Oliva3-4/+18
* armsupp.c (ARMul_CPSRAltered): Zero out bits as they're extracted from state->Cpsr, but preserve the unused bits. (ARMul_GetCPSR): Get bits preserved in state->Cpsr. (ARMul_GetSPSR, ARMul_FixCPSR): Use ARMul_GetCPSR() to get the full CPSR word.
2000-07-04* armemu.h (PSR_FBITS, PSR_SBITS, PSR_XBITS, PSR_CBITS): New.Alexandre Oliva4-30/+40
(SETPSR_F, SETPSR_S, SETPSR_X, SETPSR_C): New macros. (SETPSR, SET_INTMODE, SETCC): Removed. * armsupp.c (ARMul_FixCPSR, ARMul_FixSPSR): Do not test bit mask. Use SETPSR_* to modify PSR. (ARMul_SetCPSR): Load all bits from value. * armemu.c (ARMul_Emulate, msr): Do not test bit mask.
2000-07-04* armemu.c (ARMul_Emulate): Compute writeback value beforeAlexandre Oliva2-8/+20
loading, since the offset register may be the destination register.
2000-07-04* armdefs.h (SYSTEMBANK): Define as USERBANK.Alexandre Oliva3-8/+6
* armsupp.c (ARMul_SwitchMode): Remove SYSTEMBANK cases.
2000-06-22* armemu.c (Multiply64): Fix computation of flag N.Alexandre Oliva2-4/+5
2000-06-22* armemu.c (MultiplyAdd64): Fix computation of flag N.Alexandre Oliva2-4/+7
2000-06-20* armemu.h (NEGBRANCH): Do not overwrite the two most significantAlexandre Oliva2-1/+6
bits of the offset.
2000-05-30Add support for v4 SystemMode.Nick Clifton11-57/+159
2000-05-24Change profiling so that it is enabled by default. Re-generate everything.Andrew Cagney2-147/+162
2000-05-23Add special case handling when GDB set CPSR registerNick Clifton2-1/+12
2000-04-10* arm abort fixFrank Ch. Eigler2-3/+8
2000-03-11 Philip Blundell <philb@gnu.org> * armemu.c (LoadSMult, LoadMult): Correct handling of aborts. Patch from Allan Skillman <Allan.Skillman@arm.com>.
2000-03-23* memory corruption fixFrank Ch. Eigler2-2/+8
Wed Mar 22 15:24:21 2000 glen mccready <gkm@pobox.com> * wrapper.c (sim_open,sim_close): Copy into myname, free myname.
2000-03-02* adding forgotten entryFrank Ch. Eigler1-0/+1
2000-02-08Fix compile time warning messages.Nick Clifton10-669/+109
2000-02-05import gdb-2000-02-04 snapshotJason Molenda27-8246/+9283
2000-01-26import gdb-2000-01-26 snapshotJason Molenda2-5/+20
1999-12-07import gdb-1999-12-06 snapshotJason Molenda3-8/+26
1999-11-02import gdb-1999-11-01 snapshotJason Molenda2-0/+7
1999-10-12import gdb-1999-10-11 snapshotJason Molenda2-1/+7
1999-10-05import gdb-1999-10-04 snapshotJason Molenda2-3/+8
1999-09-09import gdb-1999-09-08 snapshotStan Shebs2-158/+153
1999-07-12import gdb-1999-07-12 snapshotJason Molenda3-1/+3
1999-05-11import gdb-1999-05-10Stan Shebs2-174/+308
generated by cgit v1.1 at 2024-11-20 02:35:49 +0000