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authorAlexandre Oliva <aoliva@redhat.com>2000-07-04 06:54:48 +0000
committerAlexandre Oliva <aoliva@redhat.com>2000-07-04 06:54:48 +0000
commit66210567f07e22e5f43e4e648358fc6b0fceac44 (patch)
tree9cd23477b574bfc5dba44887c09c018b03ac9110 /sim/arm
parente063aa3bd8d3712e37a287603d3256282c209def (diff)
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* armemu.c (ARMul_Emulate, t_undefined): Proceed to next insn.
Diffstat (limited to 'sim/arm')
-rw-r--r--sim/arm/ChangeLog2
-rw-r--r--sim/arm/armemu.c2
2 files changed, 3 insertions, 1 deletions
diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog
index 9e4bdc0..bdc2f36 100644
--- a/sim/arm/ChangeLog
+++ b/sim/arm/ChangeLog
@@ -1,5 +1,7 @@
2000-07-04 Alexandre Oliva <aoliva@redhat.com>
+ * armemu.c (ARMul_Emulate, t_undefined): Proceed to next insn.
+
* armemu.h (INSN_SIZE): New macro.
(SET_ABORT): Save CPSR in SPSR and set LR.
* armemu.c (ARMul_Emulate, isize): Set to INSN_SIZE.
diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c
index 31bd327..7152023 100644
--- a/sim/arm/armemu.c
+++ b/sim/arm/armemu.c
@@ -428,7 +428,7 @@ ARMul_Emulate26 (register ARMul_State * state)
{
case t_undefined:
ARMul_UndefInstr (state, instr); /* This is a Thumb instruction */
- break;
+ goto donext;
case t_branch: /* already processed */
goto donext;