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AgeCommit message (Expand)AuthorFilesLines
2002-05-29Set the FSR and FAR registers if a Data Abort is detected.Nick Clifton2-1/+13
2002-05-27Only perform access checks if 'check' is set.Nick Clifton7-18/+25
2002-05-27Thumb BL instruction: Do not set LR to pc + 2, it has already been advanced.Nick Clifton2-4/+11
2002-05-23When decoding a BLX(1) instruction do not add in the second bit of the baseNick Clifton2-5/+8
2002-05-21Simulate XScale BCUMOD registerNick Clifton2-3/+15
2002-05-20Add support for target specific command line switches to old-style simualtors.Nick Clifton5-250/+464
2002-05-09Uses sim callback interface for system calls in RedBoot SWI support.Nick Clifton1-8/+13
2002-05-09Support the RedBoot SWI in ARM mode and some of its system calls.Nick Clifton2-30/+109
2002-03-18Increase default memory size to 8MB.Anthony Green2-1/+5
2002-02-21 * armos.c (SWIWrite0): Use generic host_callback mechanismKeith Seitz2-31/+50
2002-02-05Modify previous patch so that it is only triggered for COFF format executables.Nick Clifton2-11/+20
2002-02-04If a v5 architecture is detected, assume it might be an XScale binary, sinceNick Clifton2-0/+15
2002-01-10Fix parameters passed to CPRead[13] and CPRead[14].Nick Clifton4-423/+478
2002-01-09General format tidy upsNick Clifton2-45/+51
2002-01-09Fix bug detected by GDB testsuite - when fetching registers more than 4Nick Clifton2-5/+19
2001-11-162001-11-16 Ben Harris <bjh21@netbsd.org>Ben Harris2-2/+8
2001-10-18Add support for XScale's coprocessor access check register.Nick Clifton5-988/+944
2001-05-11Fix handling of XScale LDRD and STRD instructions with post indexed addressin...Nick Clifton2-6/+11
2001-05-08Check Mode not Bank in order to determine rocesor mode.Nick Clifton2-1/+7
2001-04-18* XScale coprocessor support.Matthew Green6-22/+284
2001-03-20Do not enable alignment checking when loading unaligned thumb instructions.Nick Clifton2-2/+7
2001-03-06Fix BLX(1) for ThumbNick Clifton2-5/+24
2001-02-28Add support for disabling alignment checks when performing GDB interfaceNick Clifton8-44/+95
2001-02-16Remove Prefetch abort for breakpoints. Instead set the state to RESUME.Nick Clifton2-12/+7
2001-02-15Add code to preserve processor mode when a prefetchNick Clifton2-0/+14
2001-02-14Reset processor into ARM mode for any machine type except the early ARMs.Nick Clifton2-12/+20
2001-02-14remove spurious whitespaceNick Clifton1-6/+6
2001-02-14Prevent Aborts from happening whilst emulating a SWINick Clifton2-62/+83
2001-02-12Fix definition of NEGBRANCHNick Clifton2-1/+6
2001-02-01Add parentheses ready for future conbtributionNick Clifton1-39/+63
2001-02-01Update base address register after restoring register bank.Nick Clifton2-26/+64
2001-02-01Detect installation of SWI vector by running program as well as loading program.Nick Clifton5-7/+18
2000-12-19Fix test for StoreDouble Instruction.Nick Clifton2-12/+17
2000-12-11Add 0x91 as an FPE SWI.Nick Clifton2-0/+5
2000-12-08oops - remove redundant prototype introduced in previous deltaNick Clifton1-2/+0
2000-12-08Add emulation of double word load and store instructions.Nick Clifton2-3/+348
2000-12-03Suppress support of DEMON swi's in XScale mode.Nick Clifton2-71/+109
2000-11-30Add support for ARM's v5TE architecture and Intel's XScale extenstionsNick Clifton10-250/+1763
2000-09-15Replace StrongARM property with v4 and v5 properties.Nick Clifton6-90/+119
2000-08-15Compute write back value for post increment loads beforeNick Clifton2-34/+47
2000-07-142000-07-14 Fernando Nasser <fnasser@cygnus.com>Fernando Nasser2-1/+5
2000-07-142000-07-14 Fernando Nasser <fnasser@cygnus.com>Fernando Nasser2-0/+9
2000-07-04* armvirt.c (ABORTS): Do not define.Alexandre Oliva2-1/+3
2000-07-04* armdefs.h (struct ARMul_State): Add is_StrongARM.Alexandre Oliva5-11/+59
2000-07-04* armemu.c (ARMul_Emulate, t_undefined): Proceed to next insn.Alexandre Oliva2-1/+3
2000-07-04* armemu.h (INSN_SIZE): New macro.Alexandre Oliva4-45/+48
2000-07-04* armemu.c (LoadSMult): Use WriteR15() to discard the leastAlexandre Oliva2-2/+5
2000-07-04* armemu.h (WRITEDESTB): New macro.Alexandre Oliva3-37/+48
2000-07-04* armemu.h (GETSPSR): Call ARMul_GetSPSR().Alexandre Oliva3-4/+18
2000-07-04* armemu.h (PSR_FBITS, PSR_SBITS, PSR_XBITS, PSR_CBITS): New.Alexandre Oliva4-30/+40
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